?? now_direction_disp.tan.qmsg
字號:
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[2\]\$latch~10 " "Info: Node \"Direction_Disp_Row1\[2\]\$latch~10\"" { } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0} } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[4\]\$latch~10 " "Info: Node \"Direction_Disp_Row1\[4\]\$latch~10\"" { } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0} } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[5\]\$latch~10 " "Info: Node \"Direction_Disp_Row1\[5\]\$latch~10\"" { } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0} } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "Direction_Disp_Row1\[6\]\$latch~14 " "Info: Node \"Direction_Disp_Row1\[6\]\$latch~14\"" { } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0} } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 29 -1 0 } } } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clock_1KHz " "Info: Assuming node \"Clock_1KHz\" is an undefined clock" { } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 11 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clock_1KHz" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clock_1KHz register Direction_Disp_Row2\[1\]~reg0 register Direction_Disp_Row2\[4\]~reg0 172.41 MHz 5.8 ns Internal " "Info: Clock \"Clock_1KHz\" has Internal fmax of 172.41 MHz between source register \"Direction_Disp_Row2\[1\]~reg0\" and destination register \"Direction_Disp_Row2\[4\]~reg0\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Direction_Disp_Row2\[1\]~reg0 1 REG LC21 31 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC21; Fanout = 31; REG Node = 'Direction_Disp_Row2\[1\]~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.700 ns Direction_Disp_Row2\[4\]~reg0 2 REG LC16 26 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC16; Fanout = 26; REG Node = 'Direction_Disp_Row2\[4\]~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 70.27 % " "Info: Total cell delay = 2.600 ns ( 70.27 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 29.73 % " "Info: Total interconnect delay = 1.100 ns ( 29.73 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1KHz destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"Clock_1KHz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_1KHz 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'Clock_1KHz'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Clock_1KHz } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Direction_Disp_Row2\[4\]~reg0 2 REG LC16 26 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC16; Fanout = 26; REG Node = 'Direction_Disp_Row2\[4\]~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "0.100 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clock_1KHz source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"Clock_1KHz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clock_1KHz 1 CLK PIN_43 5 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 5; CLK Node = 'Clock_1KHz'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "" { Clock_1KHz } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns Direction_Disp_Row2\[1\]~reg0 2 REG LC21 31 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC21; Fanout = 31; REG Node = 'Direction_Disp_Row2\[1\]~reg0'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "0.100 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" { } { { "Now_Direction_Disp.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/Now_Direction_Disp.v" 25 -1 0 } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { Direction_Disp_Row2[1]~reg0 Direction_Disp_Row2[4]~reg0 } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[4]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[4]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp_cmp.qrpt" Compiler "Now_Direction_Disp" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/db/Now_Direction_Disp.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Slave_Control/Now_Direction_Disp/" "" "1.300 ns" { Clock_1KHz Direction_Disp_Row2[1]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clock_1KHz Clock_1KHz~out Direction_Disp_Row2[1]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } } 0}
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