?? motor_control.tan.qmsg
字號:
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Floor_Time " "Info: Assuming node \"Floor_Time\" is an undefined clock" { } { { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 15 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Floor_Time" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Floor_Time register lpm_counter:Now_Floor_rtl_0\|dffs\[0\] register lpm_counter:Now_Floor_rtl_0\|dffs\[1\] 129.87 MHz 7.7 ns Internal " "Info: Clock \"Floor_Time\" has Internal fmax of 129.87 MHz between source register \"lpm_counter:Now_Floor_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:Now_Floor_rtl_0\|dffs\[1\]\" (period= 7.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.400 ns + Longest register register " "Info: + Longest register to register delay is 5.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:Now_Floor_rtl_0\|dffs\[0\] 1 REG LC3 18 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3; Fanout = 18; REG Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.800 ns) 4.400 ns lpm_counter:Now_Floor_rtl_0\|dffs\[1\]~1740 2 COMB LC7 1 " "Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.400 ns; Loc. = LC7; Fanout = 1; COMB Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[1\]~1740'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "4.400 ns" { lpm_counter:Now_Floor_rtl_0|dffs[0] lpm_counter:Now_Floor_rtl_0|dffs[1]~1740 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 5.400 ns lpm_counter:Now_Floor_rtl_0\|dffs\[1\] 3 REG LC8 13 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 5.400 ns; Loc. = LC8; Fanout = 13; REG Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[1\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "1.000 ns" { lpm_counter:Now_Floor_rtl_0|dffs[1]~1740 lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns 70.37 % " "Info: Total cell delay = 3.800 ns ( 70.37 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 29.63 % " "Info: Total interconnect delay = 1.600 ns ( 29.63 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "5.400 ns" { lpm_counter:Now_Floor_rtl_0|dffs[0] lpm_counter:Now_Floor_rtl_0|dffs[1]~1740 lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.400 ns" { lpm_counter:Now_Floor_rtl_0|dffs[0] lpm_counter:Now_Floor_rtl_0|dffs[1]~1740 lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 1.600ns 0.000ns } { 0.000ns 2.800ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time destination 2.200 ns + Shortest register " "Info: + Shortest clock path from clock \"Floor_Time\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Floor_Time 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'Floor_Time'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Now_Floor_rtl_0\|dffs\[1\] 2 REG LC8 13 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC8; Fanout = 13; REG Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[1\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "0.400 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time source 2.200 ns - Longest register " "Info: - Longest clock path from clock \"Floor_Time\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Floor_Time 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'Floor_Time'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Now_Floor_rtl_0\|dffs\[0\] 2 REG LC3 18 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC3; Fanout = 18; REG Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "0.400 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "5.400 ns" { lpm_counter:Now_Floor_rtl_0|dffs[0] lpm_counter:Now_Floor_rtl_0|dffs[1]~1740 lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.400 ns" { lpm_counter:Now_Floor_rtl_0|dffs[0] lpm_counter:Now_Floor_rtl_0|dffs[1]~1740 lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 1.600ns 0.000ns } { 0.000ns 2.800ns 1.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[1] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[1] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "lpm_counter:Now_Floor_rtl_0\|dffs\[0\] Down_En Floor_Time 4.400 ns register " "Info: tsu for register \"lpm_counter:Now_Floor_rtl_0\|dffs\[0\]\" (data pin = \"Down_En\", clock pin = \"Floor_Time\") is 4.400 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns + Longest pin register " "Info: + Longest pin to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Down_En 1 PIN PIN_63 11 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_63; Fanout = 11; PIN Node = 'Down_En'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Down_En } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.800 ns) 4.600 ns lpm_counter:Now_Floor_rtl_0\|dffs\[0\]~1736 2 COMB LC2 1 " "Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC2; Fanout = 1; COMB Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[0\]~1736'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "4.400 ns" { Down_En lpm_counter:Now_Floor_rtl_0|dffs[0]~1736 } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 5.600 ns lpm_counter:Now_Floor_rtl_0\|dffs\[0\] 3 REG LC3 18 " "Info: 3: + IC(0.000 ns) + CELL(1.000 ns) = 5.600 ns; Loc. = LC3; Fanout = 18; REG Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "1.000 ns" { lpm_counter:Now_Floor_rtl_0|dffs[0]~1736 lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 71.43 % " "Info: Total cell delay = 4.000 ns ( 71.43 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 28.57 % " "Info: Total interconnect delay = 1.600 ns ( 28.57 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "5.600 ns" { Down_En lpm_counter:Now_Floor_rtl_0|dffs[0]~1736 lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Down_En Down_En~out lpm_counter:Now_Floor_rtl_0|dffs[0]~1736 lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.600ns 0.000ns } { 0.000ns 0.200ns 2.800ns 1.000ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.000 ns + " "Info: + Micro setup delay of destination is 1.000 ns" { } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time destination 2.200 ns - Shortest register " "Info: - Shortest clock path from clock \"Floor_Time\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Floor_Time 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'Floor_Time'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 15 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns lpm_counter:Now_Floor_rtl_0\|dffs\[0\] 2 REG LC3 18 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC3; Fanout = 18; REG Node = 'lpm_counter:Now_Floor_rtl_0\|dffs\[0\]'" { } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "0.400 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 279 12 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" { } { } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0} } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "5.600 ns" { Down_En lpm_counter:Now_Floor_rtl_0|dffs[0]~1736 lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.600 ns" { Down_En Down_En~out lpm_counter:Now_Floor_rtl_0|dffs[0]~1736 lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 1.600ns 0.000ns } { 0.000ns 0.200ns 2.800ns 1.000ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time lpm_counter:Now_Floor_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out lpm_counter:Now_Floor_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } } 0}
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