{ "Info" "ITDB_FULL_TCO_RESULT" "Floor_Time Motor_Data\[0\] Now_Direction\[0\]~reg0 9.300 ns register " "Info: tco from clock \"Floor_Time\" to destination pin \"Motor_Data\[0\]\" through register \"Now_Direction\[0\]~reg0\" is 9.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time source 2.200 ns + Longest register " "Info: + Longest clock path from clock \"Floor_Time\" to source register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Floor_Time 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'Floor_Time'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns Now_Direction\[0\]~reg0 2 REG LC9 2 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC9; Fanout = 2; REG Node = 'Now_Direction\[0\]~reg0'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "0.400 ns" { Floor_Time Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Now_Direction[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 54 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.800 ns + Longest register pin " "Info: + Longest register to pin delay is 5.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Now_Direction\[0\]~reg0 1 REG LC9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC9; Fanout = 2; REG Node = 'Now_Direction\[0\]~reg0'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 54 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(3.800 ns) 5.400 ns Now_Direction\[0\]~36 2 COMB LC19 1 " "Info: 2: + IC(1.600 ns) + CELL(3.800 ns) = 5.400 ns; Loc. = LC19; Fanout = 1; COMB Node = 'Now_Direction\[0\]~36'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "5.400 ns" { Now_Direction[0]~reg0 Now_Direction[0]~36 } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 17 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 5.800 ns Motor_Data\[0\] 3 PIN PIN_17 0 " "Info: 3: + IC(0.000 ns) + CELL(0.400 ns) = 5.800 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'Motor_Data\[0\]'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "0.400 ns" { Now_Direction[0]~36 Motor_Data[0] } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.200 ns 72.41 % " "Info: Total cell delay = 4.200 ns ( 72.41 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 27.59 % " "Info: Total interconnect delay = 1.600 ns ( 27.59 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "5.800 ns" { Now_Direction[0]~reg0 Now_Direction[0]~36 Motor_Data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.800 ns" { Now_Direction[0]~reg0 Now_Direction[0]~36 Motor_Data[0] } { 0.000ns 1.600ns 0.000ns } { 0.000ns 3.800ns 0.400ns } } }  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Now_Direction[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "5.800 ns" { Now_Direction[0]~reg0 Now_Direction[0]~36 Motor_Data[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "5.800 ns" { Now_Direction[0]~reg0 Now_Direction[0]~36 Motor_Data[0] } { 0.000ns 1.600ns 0.000ns } { 0.000ns 3.800ns 0.400ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "Now_Direction\[0\]~reg0 Down_En Floor_Time -0.800 ns register " "Info: th for register \"Now_Direction\[0\]~reg0\" (data pin = \"Down_En\", clock pin = \"Floor_Time\") is -0.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Floor_Time destination 2.200 ns + Longest register " "Info: + Longest clock path from clock \"Floor_Time\" to destination register is 2.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.800 ns) 1.800 ns Floor_Time 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(1.800 ns) = 1.800 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'Floor_Time'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Floor_Time } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 15 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.400 ns) 2.200 ns Now_Direction\[0\]~reg0 2 REG LC9 2 " "Info: 2: + IC(0.000 ns) + CELL(0.400 ns) = 2.200 ns; Loc. = LC9; Fanout = 2; REG Node = 'Now_Direction\[0\]~reg0'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "0.400 ns" { Floor_Time Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.200 ns 100.00 % " "Info: Total cell delay = 2.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Now_Direction[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "1.600 ns + " "Info: + Micro hold delay of destination is 1.600 ns" {  } { { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 54 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.600 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns Down_En 1 PIN PIN_63 11 " "Info: 1: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_63; Fanout = 11; PIN Node = 'Down_En'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "" { Down_En } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 14 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(2.800 ns) 4.600 ns Now_Direction\[0\]~reg0 2 REG LC9 2 " "Info: 2: + IC(1.600 ns) + CELL(2.800 ns) = 4.600 ns; Loc. = LC9; Fanout = 2; REG Node = 'Now_Direction\[0\]~reg0'" {  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "4.400 ns" { Down_En Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "Motor_Control.v" "" { Text "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/Motor_Control.v" 54 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.000 ns 65.22 % " "Info: Total cell delay = 3.000 ns ( 65.22 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns 34.78 % " "Info: Total interconnect delay = 1.600 ns ( 34.78 % )" {  } {  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "4.600 ns" { Down_En Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { Down_En Down_En~out Now_Direction[0]~reg0 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 0.200ns 2.800ns } } }  } 0}  } { { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "2.200 ns" { Floor_Time Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "2.200 ns" { Floor_Time Floor_Time~out Now_Direction[0]~reg0 } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.800ns 0.400ns } } } { "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" "" { Report "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control_cmp.qrpt" Compiler "Motor_Control" "UNKNOWN" "V1" "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/db/Motor_Control.quartus_db" { Floorplan "E:/戴仙金/資料/Verilog書/源代碼/lift_control/Master_Control/Motor_Control/" "" "4.600 ns" { Down_En Now_Direction[0]~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "4.600 ns" { Down_En Down_En~out Now_Direction[0]~reg0 } { 0.000ns 0.000ns 1.600ns } { 0.000ns 0.200ns 2.800ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Aug 07 14:59:31 2006 " "Info: Processing ended: Mon Aug 07 14:59:31 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}