?? test_dualport.ucf
字號:
# XSA Board FPGA pin assignment constraints
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 10 ns HIGH 50 %;
# SDRAM memory tester pin assignments
net ce_n loc=p41; # Flash RAM chip-enable
net sw2 loc=p93; # active-low pushbutton
net clk loc=p88; # main clock
net sclkfb loc=p91; # feedback SDRAM clock after PCB delays
net sclk loc=p129; # clock to SDRAM
net cke loc=p131; # SDRAM clock enable
net cs_n loc=p132; # SDRAM chip-select
net ras_n loc=p130;
net cas_n loc=p126;
net we_n loc=p123;
net dqmh loc=p124;
net dqml loc=p122;
net sData<0> loc=p95;
net sData<1> loc=p99;
net sData<2> loc=p101;
net sData<3> loc=p103;
net sData<4> loc=p113;
net sData<5> loc=p115;
net sData<6> loc=p117;
net sData<7> loc=p120;
net sData<8> loc=p121;
net sData<9> loc=p118;
net sData<10> loc=p116;
net sData<11> loc=p114;
net sData<12> loc=p112;
net sData<13> loc=p102;
net sData<14> loc=p100;
net sData<15> loc=p96;
net sAddr<0> loc=p141;
net sAddr<1> loc=p4;
net sAddr<2> loc=p6;
net sAddr<3> loc=p10;
net sAddr<4> loc=p11;
net sAddr<5> loc=p7;
net sAddr<6> loc=p5;
net sAddr<7> loc=p3;
net sAddr<8> loc=p140;
net sAddr<9> loc=p138;
net sAddr<10> loc=p139;
net sAddr<11> loc=p136;
net ba<0> loc=p134;
net ba<1> loc=p137;
net s<0> loc=p67;
net s<1> loc=p39;
net s<2> loc=p62;
net s<3> loc=p60;
net s<4> loc=p46;
net s<5> loc=p57;
net s<6> loc=p49;
net pps<6> loc=p78;
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