{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Elaboration Quartus II " "Info: Running Quartus II Analysis & Elaboration" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Jul 11 22:19:01 2008 " "Info: Processing started: Fri Jul 11 22:19:01 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Traffic -c Traffic --analysis_and_elaboration " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Traffic -c Traffic --analysis_and_elaboration" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "LEDR packed Traffic.v(12) " "Warning (10227): Verilog HDL Port Declaration warning at Traffic.v(12): data type declaration for \"LEDR\" declares packed dimensions but the port declaration declaration does not" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 12 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "LEDR Traffic.v(16) " "Info (10151): Verilog HDL Declaration information at Traffic.v(16): \"LEDR\" is declared here" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 16 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_PORT_DECL_WITHOUT_DIMS" "LEDG packed Traffic.v(13) " "Warning (10227): Verilog HDL Port Declaration warning at Traffic.v(13): data type declaration for \"LEDG\" declares packed dimensions but the port declaration declaration does not" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 13 0 0 } }  } 0 10227 "Verilog HDL Port Declaration warning at %3!s!: data type declaration for \"%1!s!\" declares %2!s! dimensions but the port declaration declaration does not" 0 0 "" 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "LEDG Traffic.v(17) " "Info (10151): Verilog HDL Declaration information at Traffic.v(17): \"LEDG\" is declared here" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 17 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Traffic.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Traffic.v" { { "Info" "ISGN_ENTITY_NAME" "1 Traffic " "Info: Found entity 1: Traffic" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Traffic " "Info: Elaborating entity \"Traffic\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_2116_UNCONVERTED" "period Traffic.v(22) " "Warning (10855): Verilog HDL warning at Traffic.v(22): initial value for variable period should be constant" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 22 0 0 } }  } 0 10855 "Verilog HDL warning at %2!s!: initial value for variable %1!s! should be constant" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Elaboration 0 s 3 s Quartus II " "Info: Quartus II Analysis & Elaboration was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Allocated 136 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 11 22:19:07 2008 " "Info: Processing ended: Fri Jul 11 22:19:07 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}