{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clc register period\[2\] register HEX0\[5\]~reg0 220.75 MHz 4.53 ns Internal " "Info: Clock \"clc\" has Internal fmax of 220.75 MHz between source register \"period\[2\]\" and destination register \"HEX0\[5\]~reg0\" (period= 4.53 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.862 ns + Longest register register " "Info: + Longest register to register delay is 0.862 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns period\[2\] 1 REG LCFF_X31_Y1_N31 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y1_N31; Fanout = 11; REG Node = 'period\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { period[2] } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.358 ns) + CELL(0.420 ns) 0.778 ns WideOr1~62 2 COMB LCCOMB_X31_Y1_N6 1 " "Info: 2: + IC(0.358 ns) + CELL(0.420 ns) = 0.778 ns; Loc. = LCCOMB_X31_Y1_N6; Fanout = 1; COMB Node = 'WideOr1~62'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.778 ns" { period[2] WideOr1~62 } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 74 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.862 ns HEX0\[5\]~reg0 3 REG LCFF_X31_Y1_N7 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.862 ns; Loc. = LCFF_X31_Y1_N7; Fanout = 1; REG Node = 'HEX0\[5\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { WideOr1~62 HEX0[5]~reg0 } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.504 ns ( 58.47 % ) " "Info: Total cell delay = 0.504 ns ( 58.47 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.358 ns ( 41.53 % ) " "Info: Total interconnect delay = 0.358 ns ( 41.53 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.862 ns" { period[2] WideOr1~62 HEX0[5]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.862 ns" { period[2] {} WideOr1~62 {} HEX0[5]~reg0 {} } { 0.000ns 0.358ns 0.000ns } { 0.000ns 0.420ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.454 ns - Smallest " "Info: - Smallest clock skew is -3.454 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clc destination 2.710 ns + Shortest register " "Info: + Shortest clock path from clock \"clc\" to destination register is 2.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clc 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clc'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clc } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clc~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clc~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clc clc~clkctrl } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.056 ns) + CELL(0.537 ns) 2.710 ns HEX0\[5\]~reg0 3 REG LCFF_X31_Y1_N7 1 " "Info: 3: + IC(1.056 ns) + CELL(0.537 ns) = 2.710 ns; Loc. = LCFF_X31_Y1_N7; Fanout = 1; REG Node = 'HEX0\[5\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { clc~clkctrl HEX0[5]~reg0 } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.68 % ) " "Info: Total cell delay = 1.536 ns ( 56.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.174 ns ( 43.32 % ) " "Info: Total interconnect delay = 1.174 ns ( 43.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { clc clc~clkctrl HEX0[5]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.710 ns" { clc {} clc~combout {} clc~clkctrl {} HEX0[5]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.056ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clc source 6.164 ns - Longest register " "Info: - Longest clock path from clock \"clc\" to source register is 6.164 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clc 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clc'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clc } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.908 ns) + CELL(0.787 ns) 3.694 ns count\[25\] 2 REG LCFF_X32_Y1_N25 2 " "Info: 2: + IC(1.908 ns) + CELL(0.787 ns) = 3.694 ns; Loc. = LCFF_X32_Y1_N25; Fanout = 2; REG Node = 'count\[25\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.695 ns" { clc count[25] } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.893 ns) + CELL(0.000 ns) 4.587 ns count\[25\]~clkctrl 3 COMB CLKCTRL_G14 4 " "Info: 3: + IC(0.893 ns) + CELL(0.000 ns) = 4.587 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'count\[25\]~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.893 ns" { count[25] count[25]~clkctrl } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.040 ns) + CELL(0.537 ns) 6.164 ns period\[2\] 4 REG LCFF_X31_Y1_N31 11 " "Info: 4: + IC(1.040 ns) + CELL(0.537 ns) = 6.164 ns; Loc. = LCFF_X31_Y1_N31; Fanout = 11; REG Node = 'period\[2\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.577 ns" { count[25]~clkctrl period[2] } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 37.69 % ) " "Info: Total cell delay = 2.323 ns ( 37.69 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.841 ns ( 62.31 % ) " "Info: Total interconnect delay = 3.841 ns ( 62.31 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.164 ns" { clc count[25] count[25]~clkctrl period[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.164 ns" { clc {} clc~combout {} count[25] {} count[25]~clkctrl {} period[2] {} } { 0.000ns 0.000ns 1.908ns 0.893ns 1.040ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { clc clc~clkctrl HEX0[5]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.710 ns" { clc {} clc~combout {} clc~clkctrl {} HEX0[5]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.056ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.164 ns" { clc count[25] count[25]~clkctrl period[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.164 ns" { clc {} clc~combout {} count[25] {} count[25]~clkctrl {} period[2] {} } { 0.000ns 0.000ns 1.908ns 0.893ns 1.040ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.862 ns" { period[2] WideOr1~62 HEX0[5]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "0.862 ns" { period[2] {} WideOr1~62 {} HEX0[5]~reg0 {} } { 0.000ns 0.358ns 0.000ns } { 0.000ns 0.420ns 0.084ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { clc clc~clkctrl HEX0[5]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.710 ns" { clc {} clc~combout {} clc~clkctrl {} HEX0[5]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.056ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "6.164 ns" { clc count[25] count[25]~clkctrl period[2] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "6.164 ns" { clc {} clc~combout {} count[25] {} count[25]~clkctrl {} period[2] {} } { 0.000ns 0.000ns 1.908ns 0.893ns 1.040ns } { 0.000ns 0.999ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clc LEDR\[0\] LEDR\[1\]~reg0 7.386 ns register " "Info: tco from clock \"clc\" to destination pin \"LEDR\[0\]\" through register \"LEDR\[1\]~reg0\" is 7.386 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clc source 2.710 ns + Longest register " "Info: + Longest clock path from clock \"clc\" to source register is 2.710 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clc 1 CLK PIN_N2 2 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clc'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clc } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clc~clkctrl 2 COMB CLKCTRL_G2 35 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clc~clkctrl'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clc clc~clkctrl } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.056 ns) + CELL(0.537 ns) 2.710 ns LEDR\[1\]~reg0 3 REG LCFF_X32_Y1_N27 2 " "Info: 3: + IC(1.056 ns) + CELL(0.537 ns) = 2.710 ns; Loc. = LCFF_X32_Y1_N27; Fanout = 2; REG Node = 'LEDR\[1\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.593 ns" { clc~clkctrl LEDR[1]~reg0 } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 56.68 % ) " "Info: Total cell delay = 1.536 ns ( 56.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.174 ns ( 43.32 % ) " "Info: Total interconnect delay = 1.174 ns ( 43.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { clc clc~clkctrl LEDR[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.710 ns" { clc {} clc~combout {} clc~clkctrl {} LEDR[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.056ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.426 ns + Longest register pin " "Info: + Longest register to pin delay is 4.426 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns LEDR\[1\]~reg0 1 REG LCFF_X32_Y1_N27 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y1_N27; Fanout = 2; REG Node = 'LEDR\[1\]~reg0'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { LEDR[1]~reg0 } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.608 ns) + CELL(2.818 ns) 4.426 ns LEDR\[0\] 2 PIN PIN_AE23 0 " "Info: 2: + IC(1.608 ns) + CELL(2.818 ns) = 4.426 ns; Loc. = PIN_AE23; Fanout = 0; PIN Node = 'LEDR\[0\]'" {  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.426 ns" { LEDR[1]~reg0 LEDR[0] } "NODE_NAME" } } { "Traffic.v" "" { Text "D:/PROGRAMING/fpga/Traffic/Traffic.v" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.818 ns ( 63.67 % ) " "Info: Total cell delay = 2.818 ns ( 63.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.608 ns ( 36.33 % ) " "Info: Total interconnect delay = 1.608 ns ( 36.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.426 ns" { LEDR[1]~reg0 LEDR[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.426 ns" { LEDR[1]~reg0 {} LEDR[0] {} } { 0.000ns 1.608ns } { 0.000ns 2.818ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.710 ns" { clc clc~clkctrl LEDR[1]~reg0 } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "2.710 ns" { clc {} clc~combout {} clc~clkctrl {} LEDR[1]~reg0 {} } { 0.000ns 0.000ns 0.118ns 1.056ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.426 ns" { LEDR[1]~reg0 LEDR[0] } "NODE_NAME" } } { "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/altera/72/quartus/bin/Technology_Viewer.qrui" "4.426 ns" { LEDR[1]~reg0 {} LEDR[0] {} } { 0.000ns 1.608ns } { 0.000ns 2.818ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 11 22:20:20 2008 " "Info: Processing ended: Fri Jul 11 22:20:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}