library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity freqdiv is
port(clock:in std_logic;
     clkout:out std_logic);	
end freqdiv;

architecture freqdiva of freqdiv is
signal clk2:std_logic:='0';
begin
  process(clock) 
  variable clk:integer :=0;
  begin		
	if(clock'event and clock='1') then
		clk:=clk+1;
		if clk>=20 then
			clk2<=not clk2;
			clk:=0;
		end if;
	end if;	
  end process;
clkout<=clk2;
end;