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ptn_Child1=Frames
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ptn_Child1=ChildFrames
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ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
ptn_Child4=Document-3
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ptn_Child1=ViewFrame-0
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DocumentCLSID={217e6880-7269-11d1-a0bf-006097df839a}
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IsActiveChildFrame=True
ptn_Child1=StateMap
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AFC_SIM_AP_NAME=sin12
AFC_PROJ_DB_PATH=D:/電子設計/VHDL/EDA技術與VHDL/LPM_ROM正弦信號發生器(12×256)/db/sin12.quartus_db
AFC_IN_REPORT=False
AFC_IN_DEBUG_SIM=False
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ptn_Child1=ViewFrame-0
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DocPathName=data_rom.vhd
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPEOPPPPPPGBAAAAAALBAAAAAACJCAAAAAPFBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap
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AFC_IN_REPORT=False
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ptn_Child1=ViewFrame-0
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DocPathName=frediv.vhd
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPEOPPPPPPCEAAAAAABFAAAAAAOLCAAAAAFJBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap
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AFC_IN_REPORT=False
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ptn_Child1=ViewFrame-0
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DocPathName=sinn.vhd
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPEOPPPPPPIFAAAAAAMGAAAAAAENCAAAAAALBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap
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AFC_IN_REPORT=False
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ptn_Child1=ViewFrame-0
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DocPathName=sin12.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
WindowPlacement=MCAAAAAAAAAAAAAABAAAAAAAPPPPPPPPPPPPPPPPMPPPPPPPEOPPPPPPOGAAAAAAHIAAAAAAKOCAAAAALMBAAAAA
IsActiveChildFrame=False
ptn_Child1=StateMap