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-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- without limitation, that your use is for the sole purpose of 
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--DA4 is DA4
DA4_or_out = APoseIn;
DA4_reg_input = DA4_or_out;
DA4 = DFFE(DA4_reg_input, GLOBAL(Clock), , , );


--DB0 is DB0
DB0_or_out = BPoseIn;
DB0_reg_input = DB0_or_out;
DB0 = DFFE(DB0_reg_input, GLOBAL(Clock), , , );


--DI3 is DI3
DI3_or_out = IndexIn;
DI3_reg_input = DI3_or_out;
DI3 = DFFE(DI3_reg_input, GLOBAL(Clock), , , );


--B1_Step[6] is SEL:inst4|Step[6]
B1_Step[6]_p1_out = SW[2] & SW[1];
B1_Step[6]_or_out = B1_Step[6]_p1_out;
B1_Step[6]_reg_input = B1_Step[6]_or_out;
B1_Step[6] = DFFE(B1_Step[6]_reg_input, GLOBAL(Clock), , , );


--B1_Step[4] is SEL:inst4|Step[4]
B1_Step[4]_or_out = SW[2];
B1_Step[4]_reg_input = B1_Step[4]_or_out;
B1_Step[4] = DFFE(B1_Step[4]_reg_input, GLOBAL(Clock), , , );


--B1_Step[2] is SEL:inst4|Step[2]
B1_Step[2]_p1_out = !SW[2] & !SW[1];
B1_Step[2]_or_out = B1_Step[2]_p1_out;
B1_Step[2]_reg_input = !(B1_Step[2]_or_out);
B1_Step[2] = DFFE(B1_Step[2]_reg_input, GLOBAL(Clock), , , );


--E1_CNT[0] is CLOCK:inst7|CNT[0]
E1_CNT[0]_p1_out = !E1_CNT[15] & !E1_CNT[14] & E1_CNT[13] & E1_CNT[12] & E1_CNT[11] & E1_CNT[10] & E1_CNT[9] & !E1_CNT[8] & E1_CNT[7] & !E1_CNT[6] & !E1_CNT[5] & !E1_CNT[4] & !E1_CNT[3] & !E1_CNT[2] & !E1_CNT[1] & !E1_CNT[0];
E1_CNT[0]_or_out = E1_CNT[0]_p1_out;
E1_CNT[0]_reg_input = !E1_CNT[0]_or_out;
E1_CNT[0] = TFFE(E1_CNT[0]_reg_input, GLOBAL(Clock), , , );


--DA1 is DA1
DA1_or_out = DA4;
DA1_reg_input = DA1_or_out;
DA1 = DFFE(DA1_reg_input, GLOBAL(Clock), , , );


--DB1 is DB1
DB1_or_out = DB0;
DB1_reg_input = DB1_or_out;
DB1 = DFFE(DB1_reg_input, GLOBAL(Clock), , , );


--B1_Step[5] is SEL:inst4|Step[5]
B1_Step[5]_p1_out = !SW[0] & !SW[1];
B1_Step[5]_or_out = B1_Step[5]_p1_out # !SW[2];
B1_Step[5]_reg_input = !(B1_Step[5]_or_out);
B1_Step[5] = DFFE(B1_Step[5]_reg_input, GLOBAL(Clock), , , );


--B1_Step[3] is SEL:inst4|Step[3]
B1_Step[3]_p1_out = SW[0] & SW[1];
B1_Step[3]_or_out = B1_Step[3]_p1_out # SW[2];
B1_Step[3]_reg_input = B1_Step[3]_or_out;
B1_Step[3] = DFFE(B1_Step[3]_reg_input, GLOBAL(Clock), , , );


--B1_Step[1] is SEL:inst4|Step[1]
B1_Step[1]_p1_out = !SW[2] & !SW[0] & !SW[1];
B1_Step[1]_or_out = B1_Step[1]_p1_out;
B1_Step[1]_reg_input = !(B1_Step[1]_or_out);
B1_Step[1] = DFFE(B1_Step[1]_reg_input, GLOBAL(Clock), , , );


--B1_Step[7] is SEL:inst4|Step[7]
B1_Step[7]_p1_out = SW[2] & SW[0] & SW[1];
B1_Step[7]_or_out = B1_Step[7]_p1_out;
B1_Step[7]_reg_input = B1_Step[7]_or_out;
B1_Step[7] = DFFE(B1_Step[7]_reg_input, GLOBAL(Clock), , , );


--DA2 is DA2
DA2_or_out = DA1;
DA2_reg_input = DA2_or_out;
DA2 = DFFE(DA2_reg_input, GLOBAL(Clock), , , );


--DB2 is DB2
DB2_or_out = DB1;
DB2_reg_input = DB2_or_out;
DB2 = DFFE(DB2_reg_input, GLOBAL(Clock), , , );


--DA3 is DA3
DA3_or_out = DA2;
DA3_reg_input = DA3_or_out;
DA3 = DFFE(DA3_reg_input, GLOBAL(Clock), , , );


--DB3 is DB3
DB3_or_out = DB2;
DB3_reg_input = DB3_or_out;
DB3 = DFFE(DB3_reg_input, GLOBAL(Clock), , , );


--JI2 is JI2
JI2_p1_out = DI3 & IndexIn & !JI2;
JI2_p2_out = !DI3 & !IndexIn & JI2;
JI2_or_out = JI2_p1_out # JI2_p2_out;
JI2_reg_input = JI2_or_out;
JI2 = TFFE(JI2_reg_input, GLOBAL(Clock), , , );


--E1_CNT[1] is CLOCK:inst7|CNT[1]
E1_CNT[1]_or_out = E1_CNT[0];
E1_CNT[1]_reg_input = E1_CNT[1] $ E1_CNT[1]_or_out;
E1_CNT[1] = DFFE(E1_CNT[1]_reg_input, GLOBAL(Clock), , , );


--JA0 is JA0
JA0_p1_out = DA2 & DA1 & DA3 & !JA0;
JA0_p2_out = !DA2 & !DA1 & !DA3 & JA0;
JA0_or_out = JA0_p1_out # JA0_p2_out;
JA0_reg_input = JA0_or_out;
JA0 = TFFE(JA0_reg_input, GLOBAL(Clock), , , );


--JB0 is JB0
JB0_p1_out = DB2 & DB1 & DB3 & !JB0;
JB0_p2_out = !DB2 & !DB1 & !DB3 & JB0;
JB0_or_out = JB0_p1_out # JB0_p2_out;
JB0_reg_input = JB0_or_out;
JB0 = TFFE(JB0_reg_input, GLOBAL(Clock), , , );


--D2X0 is D2X0
D2X0_or_out = JB0;
D2X0_reg_input = JA0 $ D2X0_or_out;
D2X0 = DFFE(D2X0_reg_input, GLOBAL(Clock), , , );


--E1_CNT[2] is CLOCK:inst7|CNT[2]
E1_CNT[2]_p1_out = E1_CNT[1] & E1_CNT[0];
E1_CNT[2]_or_out = E1_CNT[2];
E1_CNT[2]_reg_input = E1_CNT[2]_p1_out $ E1_CNT[2]_or_out;
E1_CNT[2] = DFFE(E1_CNT[2]_reg_input, GLOBAL(Clock), , , );


--D2X1 is D2X1
D2X1_or_out = D2X0;
D2X1_reg_input = D2X1_or_out;
D2X1 = DFFE(D2X1_reg_input, GLOBAL(Clock), , , );


--F1_ABXorTe is Decoder:inst9|ABXorTe
F1_ABXorTe_or_out = D2X1;
F1_ABXorTe_reg_input = F1_ABXorTe_or_out;
F1_ABXorTe = DFFE(F1_ABXorTe_reg_input, GLOBAL(Clock), , , );


--E1_CNT[3] is CLOCK:inst7|CNT[3]
E1_CNT[3]_p1_out = E1_CNT[2] & E1_CNT[1] & E1_CNT[0];
E1_CNT[3]_or_out = E1_CNT[3];
E1_CNT[3]_reg_input = E1_CNT[3]_p1_out $ E1_CNT[3]_or_out;
E1_CNT[3] = DFFE(E1_CNT[3]_reg_input, GLOBAL(Clock), , , );


--F1_CntTe[0] is Decoder:inst9|CntTe[0]
F1_CntTe[0]_p1_out = JI2 & D2X1 & !F1_ABXorTe & !F1_CntTe[0];
F1_CntTe[0]_p2_out = JI2 & !D2X1 & F1_ABXorTe & !F1_CntTe[0];
F1_CntTe[0]_p3_out = !D2X1 & !F1_ABXorTe & F1_CntTe[0];
F1_CntTe[0]_p4_out = D2X1 & F1_ABXorTe & F1_CntTe[0];
F1_CntTe[0]_or_out = F1_CntTe[0]_p1_out # F1_CntTe[0]_p2_out # F1_CntTe[0]_p3_out # F1_CntTe[0]_p4_out;
F1_CntTe[0]_reg_input = F1_CntTe[0]_or_out;
F1_CntTe[0] = DFFE(F1_CntTe[0]_reg_input, GLOBAL(Clock), , , );


--F1_AHistr is Decoder:inst9|AHistr
F1_AHistr_p1_out = JA0 & D2X1 & !F1_ABXorTe;
F1_AHistr_p2_out = JA0 & !D2X1 & F1_ABXorTe;
F1_AHistr_p3_out = !D2X1 & !F1_ABXorTe & F1_AHistr;
F1_AHistr_p4_out = D2X1 & F1_ABXorTe & F1_AHistr;
F1_AHistr_or_out = F1_AHistr_p1_out # F1_AHistr_p2_out # F1_AHistr_p3_out # F1_AHistr_p4_out;
F1_AHistr_reg_input = F1_AHistr_or_out;
F1_AHistr = DFFE(F1_AHistr_reg_input, GLOBAL(Clock), , , );


--E1_CNT[4] is CLOCK:inst7|CNT[4]
E1_CNT[4]_p1_out = E1_CNT[3] & E1_CNT[2] & E1_CNT[1] & E1_CNT[0];
E1_CNT[4]_or_out = E1_CNT[4];
E1_CNT[4]_reg_input = E1_CNT[4]_p1_out $ E1_CNT[4]_or_out;
E1_CNT[4] = DFFE(E1_CNT[4]_reg_input, GLOBAL(Clock), , , );


--F1_CntTe[1] is Decoder:inst9|CntTe[1]
F1_CntTe[1]_p0_out = !JI2 & !D2X1 & F1_ABXorTe & F1_CntTe[1];
F1_CntTe[1]_p1_out = JI2 & !D2X1 & F1_ABXorTe & !JA0 & F1_AHistr & !F1_CntTe[0];
F1_CntTe[1]_p2_out = JI2 & !D2X1 & F1_ABXorTe & !JA0 & !F1_AHistr & F1_CntTe[0];
F1_CntTe[1]_p3_out = JI2 & !D2X1 & F1_ABXorTe & JA0 & F1_AHistr & F1_CntTe[0];
F1_CntTe[1]_p4_out = !JI2 & D2X1 & !F1_ABXorTe & F1_CntTe[1];
F1_CntTe[1]_or_out = F1L05 # F1_CntTe[1]_p0_out # F1_CntTe[1]_p1_out # F1_CntTe[1]_p2_out # F1_CntTe[1]_p3_out # F1_CntTe[1]_p4_out;
F1_CntTe[1]_reg_input = F1_CntTe[1]_or_out;
F1_CntTe[1] = TFFE(F1_CntTe[1]_reg_input, GLOBAL(Clock), , , );


--E1_CNT[5] is CLOCK:inst7|CNT[5]
E1_CNT[5]_p1_out = E1_CNT[4] & E1_CNT[3] & E1_CNT[2] & E1_CNT[1] & E1_CNT[0];
E1_CNT[5]_or_out = E1_CNT[5];
E1_CNT[5]_reg_input = E1_CNT[5]_p1_out $ E1_CNT[5]_or_out;
E1_CNT[5] = DFFE(E1_CNT[5]_reg_input, GLOBAL(Clock), , , );


--E1_CNT[6] is CLOCK:inst7|CNT[6]
E1_CNT[6]_p1_out = E1_CNT[5] & E1_CNT[4] & E1_CNT[3] & E1_CNT[2] & E1_CNT[1] & E1_CNT[0];
E1_CNT[6]_or_out = E1_CNT[6];
E1_CNT[6]_reg_input = E1_CNT[6]_p1_out $ E1_CNT[6]_or_out;
E1_CNT[6] = DFFE(E1_CNT[6]_reg_input, GLOBAL(Clock), , , );