?? counter4x5.map.rpt
字號:
+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Decoder:inst9|lpm_add_sub:add_rtl_0 ;
+------------------------+-------------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-----------------------------------------------+
; LPM_WIDTH ; 24 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_9ph ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: Decoder:inst9|lpm_add_sub:add_rtl_1 ;
+------------------------+-------------+-----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+-----------------------------------------------+
; LPM_WIDTH ; 24 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_feh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: SEGCtr:inst5|lpm_add_sub:add_rtl_2 ;
+------------------------+-------------+----------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+----------------------------------------------+
; LPM_WIDTH ; 8 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_rnh ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: CLOCK:inst7|lpm_add_sub:add_rtl_3 ;
+------------------------+-------------+---------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------+---------------------------------------------+
; LPM_WIDTH ; 16 ; Untyped ;
; LPM_REPRESENTATION ; UNSIGNED ; Untyped ;
; LPM_DIRECTION ; ADD ; Untyped ;
; ONE_INPUT_IS_CONSTANT ; YES ; Untyped ;
; LPM_PIPELINE ; 0 ; Untyped ;
; MAXIMIZE_SPEED ; 5 ; Untyped ;
; REGISTERED_AT_END ; 0 ; Untyped ;
; OPTIMIZE_FOR_SPEED ; 9 ; Untyped ;
; USE_CS_BUFFERS ; 1 ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; DEVICE_FAMILY ; MAX7000S ; Untyped ;
; USE_WYS ; OFF ; Untyped ;
; STYLE ; FAST ; Untyped ;
; CBXI_PARAMETER ; add_sub_aph ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+-------------+---------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in E:/job/DelayTrigIndex/Counter4x5.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
Info: Processing started: Wed May 28 18:27:25 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Counter4x5 -c Counter4x5
Info: Found 1 design units, including 1 entities, in source file Counter4x5.bdf
Info: Found entity 1: Counter4x5
Info: Found 1 design units, including 1 entities, in source file Decoder.v
Info: Found entity 1: Decoder
Info: Found 1 design units, including 1 entities, in source file SEL.v
Info: Found entity 1: SEL
Info: Found 1 design units, including 1 entities, in source file CLOCK.v
Info: Found entity 1: CLOCK
Info: Found 1 design units, including 1 entities, in source file Dec.v
Info: Found entity 1: Dec
Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v
Info: Found entity 1: SEG7_LUT
Info: Found 1 design units, including 1 entities, in source file SEGCtr.v
Info: Found entity 1: SEGCtr
Info: Elaborating entity "Counter4x5" for the top level hierarchy
Info: Elaborating entity "Decoder" for hierarchy "Decoder:inst9"
Info: (10035) Verilog HDL or VHDL information at Decoder.v(48): object "CNT" declared but not used
Info: (10035) Verilog HDL or VHDL information at Decoder.v(49): object "PreStep" declared but not used
Info: (10035) Verilog HDL or VHDL information at Decoder.v(50): object "Step" declared but not used
Info: (10035) Verilog HDL or VHDL information at Decoder.v(52): object "Temp" declared but not used
Info: Elaborating entity "SEL" for hierarchy "SEL:inst4"
Info: Elaborating entity "CLOCK" for hierarchy "CLOCK:inst7"
Info: Elaborating entity "SEG7_LUT" for hierarchy "SEG7_LUT:inst6"
Warning: (10270) Verilog HDL statement warning at SEG7_LUT.v(8): incomplete Case Statement has no default case item
Warning: Verilog HDL Always Construct warning at SEG7_LUT.v(6): variable "oSEG" may not be assigned a new value in every possible path through the Always Construct. Variable "oSEG" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Elaborating entity "SEGCtr" for hierarchy "SEGCtr:inst5"
Warning: Verilog HDL warning at SEGCtr.v(18): port "oDIG" was previously declared with different range
Warning: Verilog HDL assignment warning at SEGCtr.v(25): truncated value with size 32 to match size of target (8)
Warning: Verilog HDL assignment warning at SEGCtr.v(27): truncated value with size 32 to match size of target (8)
Info: Power-up level of register "SEL:inst4|Step[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "SEL:inst4|Step[0]" with stuck data_in port to stuck value VCC
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/look_add.tdf
Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Ignored 70 buffer(s)
Info: Ignored 70 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin "Clock" to global clock signal
Info: Implemented 179 device resources after synthesis - the final resource count might be different
Info: Implemented 7 input pins
Info: Implemented 15 output pins
Info: Implemented 126 macrocells
Info: Implemented 31 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings
Info: Processing ended: Wed May 28 18:27:38 2008
Info: Elapsed time: 00:00:13
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