{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jul 08 14:13:52 2008 " "Info: Processing started: Tue Jul 08 14:13:52 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Counter4x5 -c Counter4x5 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Counter4x5 -c Counter4x5 --generate_functional_sim_netlist" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Counter4x5.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Counter4x5.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Counter4x5 " "Info: Found entity 1: Counter4x5" {  } { { "Counter4x5.bdf" "" { Schematic "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Counter4x5.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Decoder.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 Decoder " "Info: Found entity 1: Decoder" {  } { { "Decoder.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Decoder.v" 24 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEL.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEL.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEL " "Info: Found entity 1: SEL" {  } { { "SEL.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEL.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLOCK.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CLOCK.v" { { "Info" "ISGN_ENTITY_NAME" "1 CLOCK " "Info: Found entity 1: CLOCK" {  } { { "CLOCK.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/CLOCK.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Dec.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Dec.v" { { "Info" "ISGN_ENTITY_NAME" "1 Dec " "Info: Found entity 1: Dec" {  } { { "Dec.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Dec.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEG7_LUT.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEGCtr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEGCtr.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEGCtr " "Info: Found entity 1: SEGCtr" {  } { { "SEGCtr.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEGCtr.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Counter4x5 " "Info: Elaborating entity \"Counter4x5\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Decoder Decoder:inst9 " "Info: Elaborating entity \"Decoder\" for hierarchy \"Decoder:inst9\"" {  } { { "Counter4x5.bdf" "inst9" { Schematic "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Counter4x5.bdf" { { -328 1136 1304 -200 "inst9" "" } } } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "CNT Decoder.v(48) " "Info: (10035) Verilog HDL or VHDL information at Decoder.v(48): object \"CNT\" declared but not used" {  } { { "Decoder.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Decoder.v" 48 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "PreStep Decoder.v(49) " "Info: (10035) Verilog HDL or VHDL information at Decoder.v(49): object \"PreStep\" declared but not used" {  } { { "Decoder.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Decoder.v" 49 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "Step Decoder.v(50) " "Info: (10035) Verilog HDL or VHDL information at Decoder.v(50): object \"Step\" declared but not used" {  } { { "Decoder.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Decoder.v" 50 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "Temp Decoder.v(52) " "Info: (10035) Verilog HDL or VHDL information at Decoder.v(52): object \"Temp\" declared but not used" {  } { { "Decoder.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Decoder.v" 52 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEL SEL:inst4 " "Info: Elaborating entity \"SEL\" for hierarchy \"SEL:inst4\"" {  } { { "Counter4x5.bdf" "inst4" { Schematic "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Counter4x5.bdf" { { 8 960 1104 104 "inst4" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLOCK CLOCK:inst7 " "Info: Elaborating entity \"CLOCK\" for hierarchy \"CLOCK:inst7\"" {  } { { "Counter4x5.bdf" "inst7" { Schematic "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Counter4x5.bdf" { { 8 720 832 104 "inst7" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT:inst6 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"SEG7_LUT:inst6\"" {  } { { "Counter4x5.bdf" "inst6" { Schematic "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Counter4x5.bdf" { { 8 1616 1776 104 "inst6" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_CASE_STATEMENT" "SEG7_LUT.v(8) " "Warning: (10270) Verilog HDL statement warning at SEG7_LUT.v(8): incomplete Case Statement has no default case item" {  } { { "SEG7_LUT.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEG7_LUT.v" 8 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_ALWAYS_ID_HOLDS_VALUE" "oSEG SEG7_LUT.v(6) " "Warning: Verilog HDL Always Construct warning at SEG7_LUT.v(6): variable \"oSEG\" may not be assigned a new value in every possible path through the Always Construct.  Variable \"oSEG\" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design." {  } { { "SEG7_LUT.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEG7_LUT.v" 6 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEGCtr SEGCtr:inst5 " "Info: Elaborating entity \"SEGCtr\" for hierarchy \"SEGCtr:inst5\"" {  } { { "Counter4x5.bdf" "inst5" { Schematic "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/Counter4x5.bdf" { { 8 1368 1528 104 "inst5" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_PORT_DECLARED_WITH_DIFFERENT_RANGE" "oDIG SEGCtr.v(18) " "Warning: Verilog HDL warning at SEGCtr.v(18): port \"oDIG\" was previously declared with different range" {  } { { "SEGCtr.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEGCtr.v" 18 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 SEGCtr.v(25) " "Warning: Verilog HDL assignment warning at SEGCtr.v(25): truncated value with size 32 to match size of target (8)" {  } { { "SEGCtr.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEGCtr.v" 25 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 SEGCtr.v(27) " "Warning: Verilog HDL assignment warning at SEGCtr.v(27): truncated value with size 32 to match size of target (8)" {  } { { "SEGCtr.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEGCtr.v" 27 0 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "SEL:inst4\|Step\[0\] High " "Info: Power-up level of register \"SEL:inst4\|Step\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "SEL.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEL:inst4\|Step\[0\] data_in VCC " "Warning: Reduced register \"SEL:inst4\|Step\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "SEL.v" "" { Text "E:/WorkofMine/Ex_CPLD/DelayTrigIndex/SEL.v" 10 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 6 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Jul 08 14:13:54 2008 " "Info: Processing ended: Tue Jul 08 14:13:54 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}