?? alt_u_div_uhd.tdf
字號(hào):
--alt_u_div DEVICE_FAMILY="MAX7000S" LPM_PIPELINE=0 MAXIMIZE_SPEED=9 WIDTH_D=3 WIDTH_N=4 WIDTH_Q=4 WIDTH_R=3 denominator numerator quotient remainder
--VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_divide 2005:03:14:22:01:08:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
-- Copyright (C) 1988-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
FUNCTION add_sub_7b8 (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_8b8 (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);
FUNCTION add_sub_9b8 (dataa[2..0], datab[2..0])
RETURNS ( cout, result[2..0]);
FUNCTION add_sub_ab8 (dataa[3..0], datab[3..0])
RETURNS ( cout, result[3..0]);
--synthesis_resources = lut 7
SUBDESIGN alt_u_div_uhd
(
den_out[2..0] : output;
denominator[2..0] : input;
numerator[3..0] : input;
quotient[3..0] : output;
remainder[2..0] : output;
)
VARIABLE
add_sub_0 : add_sub_7b8;
add_sub_1 : add_sub_8b8;
add_sub_2 : add_sub_9b8;
add_sub_3 : add_sub_ab8;
DenominatorIn[19..0] : WIRE;
DenominatorIn_tmp[19..0] : WIRE;
gnd_wire : WIRE;
nose[19..0] : WIRE;
NumeratorIn[19..0] : WIRE;
NumeratorIn_tmp[19..0] : WIRE;
prestg[15..0] : WIRE;
quotient_tmp[3..0] : WIRE;
sel[14..0] : WIRE;
selnose[19..0] : WIRE;
StageIn[19..0] : WIRE;
StageIn_tmp[19..0] : WIRE;
StageOut[15..0] : WIRE;
BEGIN
add_sub_0.dataa[0..0] = NumeratorIn[3..3];
add_sub_0.datab[0..0] = DenominatorIn[0..0];
add_sub_1.dataa[] = ( StageIn[4..4], NumeratorIn[6..6]);
add_sub_1.datab[1..0] = DenominatorIn[5..4];
add_sub_2.dataa[] = ( StageIn[9..8], NumeratorIn[9..9]);
add_sub_2.datab[2..0] = DenominatorIn[10..8];
add_sub_3.dataa[] = ( StageIn[14..12], NumeratorIn[12..12]);
add_sub_3.datab[3..0] = DenominatorIn[15..12];
den_out[2..0] = DenominatorIn[14..12];
DenominatorIn[] = (gnd_wire # DenominatorIn_tmp[]);
DenominatorIn_tmp[] = ( DenominatorIn[15..0], ( gnd_wire, denominator[]));
gnd_wire = B"0";
nose[] = ( B"0000", (add_sub_3.cout # gnd_wire), B"0000", (add_sub_2.cout # gnd_wire), B"0000", (add_sub_1.cout # gnd_wire), B"0000", (add_sub_0.cout # gnd_wire));
NumeratorIn[] = (gnd_wire # NumeratorIn_tmp[]);
NumeratorIn_tmp[] = ( NumeratorIn[15..0], numerator[]);
prestg[] = ( add_sub_3.result[], GND, add_sub_2.result[], B"00", add_sub_1.result[], B"000", add_sub_0.result[]);
quotient[] = quotient_tmp[];
quotient_tmp[] = ( (! selnose[0..0]), (! selnose[5..5]), (! selnose[10..10]), (! selnose[15..15]));
remainder[2..0] = StageIn[18..16];
sel[] = ( gnd_wire, (gnd_wire # (sel[14..14] # DenominatorIn[18..18])), (gnd_wire # (sel[13..13] # DenominatorIn[17..17])), gnd_wire, (gnd_wire # (sel[11..11] # DenominatorIn[14..14])), (gnd_wire # (sel[10..10] # DenominatorIn[13..13])), gnd_wire, (gnd_wire # (sel[8..8] # DenominatorIn[10..10])), (gnd_wire # (sel[7..7] # DenominatorIn[9..9])), gnd_wire, (gnd_wire # (sel[5..5] # DenominatorIn[6..6])), (gnd_wire # (sel[4..4] # DenominatorIn[5..5])), gnd_wire, (gnd_wire # (sel[2..2] # DenominatorIn[2..2])), (gnd_wire # (sel[1..1] # DenominatorIn[1..1])));
selnose[] = ( (gnd_wire # (! nose[19..19])), ((gnd_wire # (! nose[18..18])) # sel[14..14]), ((gnd_wire # (! nose[17..17])) # sel[13..13]), ((gnd_wire # (! nose[16..16])) # sel[12..12]), (gnd_wire # (! nose[15..15])), ((gnd_wire # (! nose[14..14])) # sel[11..11]), ((gnd_wire # (! nose[13..13])) # sel[10..10]), ((gnd_wire # (! nose[12..12])) # sel[9..9]), (gnd_wire # (! nose[11..11])), ((gnd_wire # (! nose[10..10])) # sel[8..8]), ((gnd_wire # (! nose[9..9])) # sel[7..7]), ((gnd_wire # (! nose[8..8])) # sel[6..6]), (gnd_wire # (! nose[7..7])), ((gnd_wire # (! nose[6..6])) # sel[5..5]), ((gnd_wire # (! nose[5..5])) # sel[4..4]), ((gnd_wire # (! nose[4..4])) # sel[3..3]), (gnd_wire # (! nose[3..3])), ((gnd_wire # (! nose[2..2])) # sel[2..2]), ((gnd_wire # (! nose[1..1])) # sel[1..1]), ((gnd_wire # (! nose[0..0])) # sel[0..0]));
StageIn[] = (gnd_wire # StageIn_tmp[]);
StageIn_tmp[] = ( StageOut[15..0], B"0000");
StageOut[] = ( ((( StageIn[14..12], NumeratorIn[12..12]) & selnose[15..15]) # (prestg[15..12] & (! selnose[15..15]))), ((( StageIn[10..8], NumeratorIn[9..9]) & selnose[10..10]) # (prestg[11..8] & (! selnose[10..10]))), ((( StageIn[6..4], NumeratorIn[6..6]) & selnose[5..5]) # (prestg[7..4] & (! selnose[5..5]))), ((( StageIn[2..0], NumeratorIn[3..3]) & selnose[0..0]) # (prestg[3..0] & (! selnose[0..0]))));
END;
--VALID FILE
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