?? convert.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity convert is
PORT(
Scan : in STD_LOGIC_VECTOR(7 DOWNTO 0);
prepared : in STD_LOGIC;
clr : in STD_LOGIC;
data : out STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end convert;
architecture behav of convert is
component mydff is
port(
clock : in std_logic;
data : in std_logic;
q : out std_logic
);
end component;
signal tmpASCII:integer range 0 to 16#7F#;
signal ASCII : STD_LOGIC_VECTOR(7 DOWNTO 0);
signal keypressed_D : std_logic:='0';
signal shifted_D : std_logic:='0';
signal capslocked_D : std_logic:='0';
signal keypressed : std_logic:='0';
signal shifted : std_logic:='0';
signal capslocked : std_logic:='0';
begin
keypressed_D<='1' when Scan=x"F0"
else '0';
shifted_D<=
'0' when CLR='0' else
not shifted when (scan=x"12" or scan=x"59") else
shifted;
capslocked_D<=
'0' when clr='0' else
not capslocked when scan=x"58" and keypressed='1' else
capslocked;
tmpASCii<=
16#09# when scan="00001101" else
16#60# when scan="00001110" and shifted='0' else
16#7E# when scan="00001110" and shifted='1' else
16#51# when scan="00010101" else
16#31# when scan="00010110" and shifted='0' else
16#21# when scan="00010110" and shifted='1' else
16#5A# when scan="00011010" else
16#53# when scan="00011011" else
16#41# when scan="00011100" else
16#57# when scan="00011101" else
16#32# when scan="00011110" and shifted='0' else
16#40# when scan="00010110" and shifted='1' else
16#43# when scan="00100001" else
16#58# when scan="00100010" else
16#44# when scan="00100011" else
16#45# when scan="00100100" else
16#34# when scan="00100101" and shifted='0' else
16#24# when scan="00100101" and shifted='1' else
16#33# when scan="00100110" and shifted='0' else
16#23# when scan="00100110" and shifted='1' else
16#20# when scan="00101001" else
16#56# when scan="00101010" else
16#46# when scan="00101011" else
16#54# when scan="00101100" else
16#52# when scan="00101101" else
16#35# when scan="00101110" and shifted='0' else
16#25# when scan="00101110" and shifted='1' else
16#4E# when scan="00110001" else
16#42# when scan="00110010" else
16#48# when scan="00110011" else
16#47# when scan="00110100" else
16#59# when scan="00110101" else
16#36# when scan="00110110" and shifted='0' else
16#5E# when scan="00110110" and shifted='1' else
16#4D# when scan="00111010" else
16#4A# when scan="00111011" else
16#55# when scan="00111100" else
16#37# when scan="00111101" and shifted='0' else
16#26# when scan="00111101" and shifted='1' else
16#38# when scan="00111110" and shifted='0' else
16#2A# when scan="00111110" and shifted='1' else
16#2C# when scan="01000001" and shifted='0' else
16#3C# when scan="01000001" and shifted='1' else
16#4B# when scan="01000010" else
16#49# when scan="01000011" else
16#4F# when scan="01000100" else
16#30# when scan="01000101" and shifted='0' else
16#29# when scan="01000101" and shifted='1' else
16#39# when scan="01000110" and shifted='0' else
16#28# when scan="01000110" and shifted='1' else
16#2E# when scan="01001001" and shifted='0' else
16#3E# when scan="01001001" and shifted='1' else
16#2F# when scan="01001010" and shifted='0' else
16#3F# when scan="01001010" and shifted='1' else
16#4C# when scan="01001011" else
16#3B# when scan="01001100" and shifted='0' else
16#3A# when scan="01001100" and shifted='1' else
16#50# when scan="01001101" else
16#2D# when scan="01001110" and shifted='0' else
16#5F# when scan="01001110" and shifted='1' else
16#27# when scan="01010010" and shifted='0' else
16#22# when scan="01010010" and shifted='1' else
16#5B# when scan="01010100" and shifted='0' else
16#7B# when scan="01010100" and shifted='1' else
16#3D# when scan="01010101" and shifted='0' else
16#2B# when scan="01010101" and shifted='1' else
16#0D# when scan="01011010" else
16#5D# when scan="01011011" and shifted='0' else
16#7D# when scan="01011011" and shifted='1' else
16#5C# when scan="01011101" and shifted='0' else
16#7C# when scan="01011101" and shifted='1' else
16#08# when scan="01100110" else
16#1B# when scan="01110110" ;
ASCII<=conv_std_logic_vector(tmpAscii+16#20#,8)
when((shifted='0' and CapsLocked='0') or (shifted='1' and CapsLocked='1'))
and (tmpAscii>16#40#) and (tmpAscii<=16#5A#)
and keypressed='1' else
conv_std_logic_vector(tmpAscii,8) when keypressed='1' else
"10000000";
dff_component1:mydff
port map(
data=>keypressed_D,
q=>keypressed,
clock=>prepared
);
dff_component2:mydff
port map(
data=>shifted_D,
q=>shifted,
clock=>prepared
);
dff_component3:mydff
port map(
data=>CapsLocked_D,
q=>CapsLocked,
clock=>prepared
);
data(7 downto 0)<=ASCII;
end behav;
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