?? cnt10.rpt
字號:
- 3 - A 13 DFFE + 1 2 1 4 cqi1 (:11)
- 8 - A 23 DFFE + 1 0 1 5 cqi0 (:12)
- 6 - A 13 OR2 s 1 3 0 3 ~126~1
- 2 - A 13 OR2 s ! 0 2 0 1 ~173~1
- 5 - A 13 AND2 0 4 1 0 :173
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zhangshuhua\szmb\cnt10.rpt
cnt10
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zhangshuhua\szmb\cnt10.rpt
cnt10
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 clk
Device-Specific Information: f:\zhangshuhua\szmb\cnt10.rpt
cnt10
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 clr
Device-Specific Information: f:\zhangshuhua\szmb\cnt10.rpt
cnt10
** EQUATIONS **
clk : INPUT;
clr : INPUT;
ena : INPUT;
-- Node name is 'carry_out'
-- Equation name is 'carry_out', type is output
carry_out = _LC5_A13;
-- Node name is ':12' = 'cqi0'
-- Equation name is 'cqi0', location is LC8_A23, type is buried.
cqi0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = cqi0 & !ena
# !cqi0 & ena;
-- Node name is ':11' = 'cqi1'
-- Equation name is 'cqi1', location is LC3_A13, type is buried.
cqi1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !cqi0 & cqi1 & _LC6_A13
# cqi0 & !cqi1 & _LC6_A13
# cqi1 & !ena;
-- Node name is ':10' = 'cqi2'
-- Equation name is 'cqi2', location is LC1_A13, type is buried.
cqi2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = cqi2 & _LC6_A13 & !_LC7_A13
# !cqi2 & _LC6_A13 & _LC7_A13
# cqi2 & !ena;
-- Node name is ':9' = 'cqi3'
-- Equation name is 'cqi3', location is LC4_A13, type is buried.
cqi3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = cqi3 & _LC6_A13 & !_LC8_A13
# !cqi3 & _LC6_A13 & _LC8_A13
# cqi3 & !ena;
-- Node name is 'cq0'
-- Equation name is 'cq0', type is output
cq0 = cqi0;
-- Node name is 'cq1'
-- Equation name is 'cq1', type is output
cq1 = cqi1;
-- Node name is 'cq2'
-- Equation name is 'cq2', type is output
cq2 = cqi2;
-- Node name is 'cq3'
-- Equation name is 'cq3', type is output
cq3 = cqi3;
-- Node name is '|LPM_ADD_SUB:73|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A13', type is buried
_LC7_A13 = LCELL( _EQ005);
_EQ005 = cqi0 & cqi1;
-- Node name is '|LPM_ADD_SUB:73|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A13', type is buried
_LC8_A13 = LCELL( _EQ006);
_EQ006 = cqi0 & cqi1 & cqi2;
-- Node name is '~126~1'
-- Equation name is '~126~1', location is LC6_A13, type is buried.
-- synthesized logic cell
_LC6_A13 = LCELL( _EQ007);
_EQ007 = !cqi3 & ena
# ena & !_LC2_A13
# !cqi0 & ena;
-- Node name is '~173~1'
-- Equation name is '~173~1', location is LC2_A13, type is buried.
-- synthesized logic cell
!_LC2_A13 = _LC2_A13~NOT;
_LC2_A13~NOT = LCELL( _EQ008);
_EQ008 = cqi2
# cqi1;
-- Node name is ':173'
-- Equation name is '_LC5_A13', type is buried
_LC5_A13 = LCELL( _EQ009);
_EQ009 = !cqi0 & !cqi1 & !cqi2 & !cqi3;
Project Information f:\zhangshuhua\szmb\cnt10.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,649K
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