signal nret_st0       : std_logic := '0';signal ret_st1        : std_logic := '0';signal ret_st2        : std_logic := '0';signal ret_st3        : std_logic := '0';signal nreti_st0      : std_logic := '0';signal reti_st1       : std_logic := '0';signal reti_st2       : std_logic := '0';signal reti_st3       : std_logic := '0';signal brxx_st        : std_logic := '0';  -- BRANCHESsignal adiw_st        : std_logic := '0';signal sbiw_st        : std_logic := '0';signal nskip_inst_st0 : std_logic := '0';signal skip_inst_st1  : std_logic := '0';signal skip_inst_st2  : std_logic := '0';  -- ALL SKIP INSTRUCTIONS SBRS/SBRC/SBIS/SBIC/CPSE signal skip_inst_start  : std_logic := '0';signal nlpm_st0       : std_logic := '0';signal lpm_st1        : std_logic := '0';signal lpm_st2        : std_logic := '0';signal nelpm_st0      : std_logic := '0';signal elpm_st1       : std_logic := '0';signal elpm_st2       : std_logic := '0';signal nsts_st0       : std_logic := '0';signal sts_st1        : std_logic := '0';signal sts_st2        : std_logic := '0';signal nlds_st0       : std_logic := '0';signal lds_st1        : std_logic := '0';signal lds_st2        : std_logic := '0';signal st_st          : std_logic := '0';signal ld_st          : std_logic := '0';signal sbi_st         : std_logic := '0';signal cbi_st         : std_logic := '0';signal push_st        : std_logic := '0';signal pop_st	      : std_logic := '0';-- INTERNAL STATE MACHINESsignal nop_insert_st  : std_logic := '0';signal cpu_busy       : std_logic :='0';-- INTERNAL COPIES OF OUTPUTSsignal pc_int              : std_logic_vector (15 downto 0):=(others =>'0');signal adr_int             : std_logic_vector (5 downto 0):=(others =>'0');signal iore_int 		   : std_logic := '0';signal iowe_int            : std_logic := '0';signal ramadr_int          : std_logic_vector (15 downto 0):=(others =>'0');signal ramre_int           : std_logic := '0';signal ramwe_int           : std_logic := '0';signal dbusout_int         : std_logic_vector (7 downto 0):=(others =>'0');-- COMMAND REGISTERsignal instruction_reg      : std_logic_vector (15 downto 0):=(others =>'0'); -- OUTPUT OF THE INSTRUCTION REGISTERsignal instruction_code_reg : std_logic_vector (15 downto 0):=(others =>'0'); -- OUTPUT OF THE INSTRUCTION REGISTER WITH NOP INSERTIONsignal instruction_reg_ena  : std_logic := '0';                               -- CLOCK ENABLE-- IRQ INTERNAL LOGICsignal irq_int : std_logic;signal irq_vector_adr : std_logic_vector(15 downto 0):=(others =>'0');signal irq_pr_encoder : std_logic_vector(6 downto 0):=(others =>'0');-- INTERRUPT RELATING REGISTERSsignal pc_for_interrupt : std_logic_vector(15 downto 0):=(others =>'0'); -- DATA EXTRACTOR SIGNALSsignal dex_dat8_immed  : std_logic_vector (7 downto 0):=(others =>'0');  -- IMMEDIATE CONSTANT (DATA) -> ANDI,ORI,SUBI,SBCI,CPI,LDIsignal dex_dat6_immed  : std_logic_vector (5 downto 0):=(others =>'0');  -- IMMEDIATE CONSTANT (DATA) -> ADIW,SBIWsignal dex_adr12mem_s  : std_logic_vector (11 downto 0):=(others =>'0'); -- RELATIVE ADDRESS (SIGNED) -> RCALL,RJMPsignal dex_adr6port    : std_logic_vector (5 downto 0):=(others =>'0');  -- I/O PORT ADDRESS -> IN,OUTsignal dex_adr5port    : std_logic_vector (4 downto 0):=(others =>'0');  -- I/O PORT ADDRESS -> CBI,SBI,SBIC,SBISsignal dex_adr_disp    : std_logic_vector (5 downto 0):=(others =>'0');  -- DISPLACEMENT FO ADDDRESS -> STD,LDDsignal dex_condition   : std_logic_vector (2 downto 0):=(others =>'0');  -- CONDITION -> BRBC,BRBSsignal dex_bitnum_sreg : std_logic_vector (2 downto 0):=(others =>'0');  -- NUMBER OF BIT IN SREG -> BCLR,BSETsignal dex_adrreg_r    : std_logic_vector (4 downto 0):=(others =>'0');  -- SOURCE REGISTER ADDRESS -> .......signal dex_adrreg_d    : std_logic_vector (4 downto 0):=(others =>'0');  -- DESTINATION REGISTER ADDRESS -> ......signal dex_bitop_bitnum : std_logic_vector(2 downto 0):=(others =>'0');  -- NUMBER OF BIT FOR BIT ORIENTEDE OPERATION -> BST/BLD+SBI/CBI+SBIC/SBIS+SBRC/SBRS !! CHECKEDsignal dex_brxx_offset : std_logic_vector (6 downto 0):=(others =>'0');  -- RELATIVE ADDRESS (SIGNED) -> BRBC,BRBS !! CHECKEDsignal dex_adiw_sbiw_reg_adr  : std_logic_vector (1 downto 0):=(others =>'0');  -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONSsignal dex_adrreg_d_latched : std_logic_vector (4 downto 0):=(others =>'0');   --  STORE ADDRESS OF DESTINATION REGISTER FOR LDS/STS/POP INSTRUCTIONSsignal gp_reg_tmp           : std_logic_vector (7 downto 0):=(others =>'0');   --  STORE DATA FROM THE REGISTERS FOR STS,ST INSTRUCTIONSsignal cbi_sbi_io_adr_tmp   : std_logic_vector (4 downto 0):=(others =>'0');   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTIONsignal cbi_sbi_bit_num_tmp  : std_logic_vector (2 downto 0):=(others =>'0');   --  STORE ADDRESS OF I/O PORT FOR CBI/SBI INSTRUCTION-- INSTRUCTIONS DECODER SIGNALSsignal idc_adc     : std_logic; -- INSTRUCTION ADCsignal idc_add     : std_logic; -- INSTRUCTION ADDsignal idc_adiw    : std_logic; -- INSTRUCTION ADIWsignal idc_and     : std_logic; -- INSTRUCTION ANDsignal idc_andi    : std_logic; -- INSTRUCTION ANDIsignal idc_asr     : std_logic; -- INSTRUCTION ASRsignal idc_bclr    : std_logic; -- INSTRUCTION BCLRsignal idc_bld     : std_logic; -- INSTRUCTION BLDsignal idc_brbc    : std_logic; -- INSTRUCTION BRBCsignal idc_brbs    : std_logic; -- INSTRUCTION BRBSsignal idc_bset    : std_logic; -- INSTRUCTION BSETsignal idc_bst     : std_logic; -- INSTRUCTION BSTsignal idc_call    : std_logic; -- INSTRUCTION CALLsignal idc_cbi     : std_logic; -- INSTRUCTION CBIsignal idc_com     : std_logic; -- INSTRUCTION COMsignal idc_cp      : std_logic; -- INSTRUCTION CPsignal idc_cpc     : std_logic; -- INSTRUCTION CPCsignal idc_cpi     : std_logic; -- INSTRUCTION CPIsignal idc_cpse    : std_logic; -- INSTRUCTION CPSEsignal idc_dec     : std_logic; -- INSTRUCTION DECsignal idc_elpm    : std_logic; -- INSTRUCTION ELPMsignal idc_eor     : std_logic; -- INSTRUCTION EORsignal idc_icall   : std_logic; -- INSTRUCTION ICALLsignal idc_ijmp    : std_logic; -- INSTRUCTION IJMPsignal idc_in      : std_logic; -- INSTRUCTION INsignal idc_inc     : std_logic; -- INSTRUCTION INCsignal idc_jmp     : std_logic; -- INSTRUCTION JMPsignal idc_ld_x    : std_logic; -- INSTRUCTION LD Rx,X ; LD Rx,X+ ;LD Rx,-Xsignal idc_ld_y    : std_logic; -- INSTRUCTION LD Rx,Y ; LD Rx,Y+ ;LD Rx,-Ysignal idc_ldd_y   : std_logic; -- INSTRUCTION LDD Rx,Y+qsignal idc_ld_z    : std_logic; -- INSTRUCTION LD Rx,Z ; LD Rx,Z+ ;LD Rx,-Zsignal idc_ldd_z   : std_logic; -- INSTRUCTION LDD Rx,Z+qsignal idc_ldi     : std_logic; -- INSTRUCTION LDIsignal idc_lds     : std_logic; -- INSTRUCTION LDSsignal idc_lpm     : std_logic; -- INSTRUCTION LPMsignal idc_lsr     : std_logic; -- INSTRUCTION LSRsignal idc_mov     : std_logic; -- INSTRUCTION MOVsignal idc_mul     : std_logic; -- INSTRUCTION MULsignal idc_neg     : std_logic; -- INSTRUCTION NEGsignal idc_nop     : std_logic; -- INSTRUCTION NOPsignal idc_or      : std_logic; -- INSTRUCTION ORsignal idc_ori     : std_logic; -- INSTRUCTION ORIsignal idc_out     : std_logic; -- INSTRUCTION OUTsignal idc_pop     : std_logic; -- INSTRUCTION POPsignal idc_push    : std_logic; -- INSTRUCTION PUSHsignal idc_rcall   : std_logic; -- INSTRUCTION RCALLsignal idc_ret     : std_logic; -- INSTRUCTION RETsignal idc_reti    : std_logic; -- INSTRUCTION RETIsignal idc_rjmp    : std_logic; -- INSTRUCTION RJMPsignal idc_ror     : std_logic; -- INSTRUCTION RORsignal idc_sbc     : std_logic; -- INSTRUCTION SBCsignal idc_sbci    : std_logic; -- INSTRUCTION SBCIsignal idc_sbi     : std_logic; -- INSTRUCTION SBIsignal idc_sbic    : std_logic; -- INSTRUCTION SBICsignal idc_sbis    : std_logic; -- INSTRUCTION SBISsignal idc_sbiw    : std_logic; -- INSTRUCTION SBIWsignal idc_sbrc    : std_logic; -- INSTRUCTION SBRCsignal idc_sbrs    : std_logic; -- INSTRUCTION SBRSsignal idc_sleep   : std_logic; -- INSTRUCTION SLEEPsignal idc_st_x    : std_logic; -- INSTRUCTION LD X,Rx ; LD X+,Rx ;LD -X,Rxsignal idc_st_y    : std_logic; -- INSTRUCTION LD Y,Rx ; LD Y+,Rx ;LD -Y,Rxsignal idc_std_y   : std_logic; -- INSTRUCTION LDD Y+q,Rxsignal idc_st_z    : std_logic; -- INSTRUCTION LD Z,Rx ; LD Z+,Rx ;LD -Z,Rxsignal idc_std_z   : std_logic; -- INSTRUCTION LDD Z+q,Rxsignal idc_sts     : std_logic; -- INSTRUCTION STSsignal idc_sub     : std_logic; -- INSTRUCTION SUBsignal idc_subi    : std_logic; -- INSTRUCTION SUBIsignal idc_swap    : std_logic; -- INSTRUCTION SWAPsignal idc_wdr     : std_logic; -- INSTRUCTION WDR-- ADDITIONAL SIGNALSsignal idc_psinc   :  std_logic; -- POST INCREMENT FLAG FOR LD,ST INSTRUCTIONSsignal idc_prdec   :  std_logic; -- PRE DECREMENT  FLAG FOR LD,ST INSTRUCTIONS-- ##################################################-- SREG FLAGS WRITE ENABLE SIGNALSalias sreg_c_wr_en  : std_logic is sreg_fl_wr_en(0);alias sreg_z_wr_en  : std_logic is sreg_fl_wr_en(1);alias sreg_n_wr_en  : std_logic is sreg_fl_wr_en(2);alias sreg_v_wr_en  : std_logic is sreg_fl_wr_en(3);alias sreg_s_wr_en  : std_logic is sreg_fl_wr_en(4);alias sreg_h_wr_en  : std_logic is sreg_fl_wr_en(5);alias sreg_t_wr_en  : std_logic is sreg_fl_wr_en(6);alias sreg_i_wr_en  : std_logic is sreg_fl_wr_en(7);signal sreg_bop_wr_en : std_logic_vector (7 downto 0);                signal sreg_adr_eq  : std_logic;-- &&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&&begin-- INSTRUCTION FETCHinstruction_reg_ena <= '1'; -- FOR TESTinstruction_fetch:process(clk,nrst)beginif nrst='0' then                              -- RESETinstruction_reg <= (others => '0');elsif (clk='1' and clk'event) then            -- CLOCKif instruction_reg_ena='1' then               -- CLOCK ENABLEinstruction_reg <= inst;end if;end if;end process;-- TWO WORDS INSTRUCTION DETECTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)two_word_inst <= '1' when ((instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010111") or    -- CALL (instruction_reg(15 downto 9)&instruction_reg(3 downto 1)="1001010110")) or   -- JMP (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010000000") or -- LDS (instruction_reg(15 downto 9)&instruction_reg(3 downto 0) = "10010010000")    -- STS   else '0';  -- TO DETECT CALL/JMP/LDS/STS INSTRUCTIONS FOR SBRS/SBRC/SBIS/SBIC/CPSE		-- DATA EXTRACTOR (CONNECTED DIRECTLY TO THE INSTRUCTION REGISTER)dex_dat8_immed <= instruction_reg(11 downto 8) & instruction_reg(3 downto 0);dex_dat6_immed <= instruction_reg(7 downto 6) & instruction_reg(3 downto 0);dex_adr12mem_s <= instruction_reg(11 downto 0); dex_adr6port <= instruction_reg(10 downto 9) & instruction_reg(3 downto 0);    dex_adr5port <= instruction_reg(7 downto 3);  dex_adr_disp <= instruction_reg(13) & instruction_reg(11 downto 10) & instruction_reg(2 downto 0);      dex_condition <= instruction_reg(2 downto 0);   dex_bitop_bitnum <= instruction_reg(2 downto 0);      -- NUMBER(POSITION) OF TESTING BIT IN SBRC/SBRS/SBIC/SBIS INSTRUCTIONdex_bitnum_sreg <= instruction_reg(6 downto 4);    dex_adrreg_r  <=  instruction_reg(9) & instruction_reg(3 downto 0);dex_adrreg_d  <= instruction_reg(8 downto 4);     dex_brxx_offset <= instruction_reg(9 downto 3);       -- OFFSET FOR BRBC/BRBS     dex_adiw_sbiw_reg_adr <= instruction_reg(5 downto 4); -- ADDRESS OF THE LOW REGISTER FOR ADIW/SBIW INSTRUCTIONS--dex_adrindreg <= instruction_reg(3 downto 2);     -- LATCH Rd ADDDRESS FOR LDS/STS/POP INSTRUCTIONSlatcht_rd_adr:process(clk,nrst)beginif nrst ='0' thendex_adrreg_d_latched <= (others => '0');elsif (clk='1' and clk'event) thenif ((idc_ld_x or idc_ld_y or idc_ldd_y or idc_ld_z or idc_ldd_z) or idc_sts or 	(idc_st_x  or idc_st_y or idc_std_y or idc_st_z or idc_std_z)or idc_lds or 	idc_pop)='1' then     -- CLOCK ENABLEdex_adrreg_d_latched <= dex_adrreg_d;end if;end if;end process;-- +++++++++++++++++++++++++++++++++++++++++++++++++-- R24:R25/R26:R27/R28:R29/R30:R31 ADIW/SBIW  ADDRESS CONTROL LOGICadiw_sbiw_encoder_out <= "11"&dex_adiw_sbiw_reg_adr&'0';adiw_sbiw_high_reg_adr:process(clk,nrst)beginif nrst ='0' thenadiw_sbiw_encoder_mux_out <= (others=>'0'); elsif(clk='1' and clk'event) thenadiw_sbiw_encoder_mux_out <= adiw_sbiw_encoder_out +1;end if;end process;	-- ##########################-- NOP INSERT STATE MACHINEinstruction_code_reg <= instruction_reg when nop_insert_st='0' else (others => '0');	--nop_insertion:process(clk,nrst)--begin--if nrst='0' then                       -- RESET--nop_insert_st <='0';--elsif (clk='1' and clk'event) then       -- CLOCK--end if;--end process;nop_insert_st <= adiw_st or sbiw_st or cbi_st or sbi_st or rjmp_st or ijmp_st or pop_st or push_st or