--**********************************************************************************************-- Timers/Counters Block Peripheral for the AVR Core-- Version 1.01 -- Modified 20.05.2003-- Synchronizer for EXT1/EXT2/Tosc1 inputs was added-- Designed by Ruslan Lepetenok--**********************************************************************************************library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_unsigned.all;use WORK.AVRuCPackage.all;entity Timer_Counter is port(	                   -- AVR Control               ireset         : in std_logic;               cp2	          : in std_logic;               adr            : in std_logic_vector(5 downto 0);               dbus_in        : in std_logic_vector(7 downto 0);               dbus_out       : out std_logic_vector(7 downto 0);               iore           : in std_logic;               iowe           : in std_logic;               out_en         : out std_logic;                        --Timer/Counters               EXT1           : in std_logic;               EXT2           : in std_logic;			   Tosc1	      : in std_logic;			   OC0_PWM0       : out std_logic;			   OC1A_PWM1A     : out std_logic;			   OC1B_PWM1B     : out std_logic;			   OC2_PWM2       : out std_logic;			   		   			           --IRQ               TC0OvfIRQ      : out std_logic;			   TC0OvfIRQ_Ack  : in std_logic;			   TC0CmpIRQ      : out std_logic;			   TC0CmpIRQ_Ack  : in std_logic;			   TC2OvfIRQ      : out std_logic;			   TC2OvfIRQ_Ack  : in std_logic;			   TC2CmpIRQ      : out std_logic;			   TC2CmpIRQ_Ack  : in std_logic;			   TC1OvfIRQ      : out std_logic;			   TC1OvfIRQ_Ack  : in std_logic;			   TC1CmpAIRQ     : out std_logic;			   TC1CmpAIRQ_Ack : in std_logic;			   TC1CmpBIRQ     : out std_logic;			   TC1CmpBIRQ_Ack : in std_logic;			   			   TC1ICIRQ       : out std_logic;			   TC1ICIRQ_Ack   : in std_logic);end Timer_Counter;architecture rtl of Timer_Counter is-- Copies of the external signalssignal OC0_PWM0_Int   :	std_logic := '0';signal OC2_PWM2_Int   :	std_logic := '0';-- Registerssignal TCCR0  : std_logic_vector(7 downto 0) := (others => '0');signal TCCR1A : std_logic_vector(7 downto 0) := (others => '0');signal TCCR1B : std_logic_vector(7 downto 0) := (others => '0');signal TCCR2  : std_logic_vector(7 downto 0) := (others => '0');signal ASSR   : std_logic_vector(7 downto 0) := (others => '0'); -- Asynchronous status register (for TCNT0)signal TIMSK  : std_logic_vector(7 downto 0) := (others => '0');signal TIFR   : std_logic_vector(7 downto 0) := (others => '0');signal TCNT0  : std_logic_vector(7 downto 0) := (others => '0');signal TCNT2  : std_logic_vector(7 downto 0) := (others => '0');signal OCR0   : std_logic_vector(7 downto 0) := (others => '0');signal OCR2   : std_logic_vector(7 downto 0) := (others => '0');signal TCNT1H : std_logic_vector(7 downto 0) := (others => '0');signal TCNT1L : std_logic_vector(7 downto 0) := (others => '0');signal OCR1AH : std_logic_vector(7 downto 0) := (others => '0');signal OCR1AL : std_logic_vector(7 downto 0) := (others => '0');signal OCR1BH : std_logic_vector(7 downto 0) := (others => '0');signal OCR1BL : std_logic_vector(7 downto 0) := (others => '0');signal ICR1AH : std_logic_vector(7 downto 0) := (others => '0');signal ICR1AL : std_logic_vector(7 downto 0) := (others => '0');signal TCCR0_Sel  : std_logic := '0';signal TCCR1A_Sel : std_logic := '0';signal TCCR1B_Sel : std_logic := '0';signal TCCR2_Sel  : std_logic := '0';signal ASSR_Sel   : std_logic := '0';signal TIMSK_Sel  : std_logic := '0';signal TIFR_Sel   : std_logic := '0';signal TCNT0_Sel  : std_logic := '0';signal TCNT2_Sel  : std_logic := '0';signal OCR0_Sel   : std_logic := '0';signal OCR2_Sel   : std_logic := '0';signal TCNT1H_Sel : std_logic := '0';signal TCNT1L_Sel : std_logic := '0';signal OCR1AH_Sel : std_logic := '0';signal OCR1AL_Sel : std_logic := '0';signal OCR1BH_Sel : std_logic := '0';signal OCR1BL_Sel : std_logic := '0';signal ICR1AH_Sel : std_logic := '0';signal ICR1AL_Sel : std_logic := '0';  -- TCCR0 Bitsalias CS00  : std_logic is TCCR0(0);alias CS01  : std_logic is TCCR0(1);alias CS02  : std_logic is TCCR0(2);alias CTC0  : std_logic is TCCR0(3);alias COM00 : std_logic is TCCR0(4);alias COM01 : std_logic is TCCR0(5);alias PWM0  : std_logic is TCCR0(6);  -- TCCR1A Bitsalias PWM10  : std_logic is TCCR1A(0);alias PWM11  : std_logic is TCCR1A(1);alias COM1B0 : std_logic is TCCR1A(4);alias COM1B1 : std_logic is TCCR1A(5);alias COM1A0 : std_logic is TCCR1A(4);alias COM1A1 : std_logic is TCCR1A(5);  -- TCCR1B Bitsalias CS10  : std_logic is TCCR1A(0);alias CS11  : std_logic is TCCR1A(1);alias CS12  : std_logic is TCCR1A(2);alias CTC1  : std_logic is TCCR1A(3);alias ICES1 : std_logic is TCCR1A(6);alias ICNC1 : std_logic is TCCR1A(7);  -- TCCR2 Bitsalias CS20  : std_logic is TCCR2(0);alias CS21  : std_logic is TCCR2(1);alias CS22  : std_logic is TCCR2(2);alias CTC2  : std_logic is TCCR2(3);alias COM20 : std_logic is TCCR2(4);alias COM21 : std_logic is TCCR2(5);alias PWM2  : std_logic is TCCR2(6);-- ASSR bitsalias TCR0UB  : std_logic is ASSR(0);alias OCR0UB  : std_logic is ASSR(1);alias TCN0UB  : std_logic is ASSR(2);alias AS0     : std_logic is ASSR(3);-- TIMSK bitsalias TOIE0     : std_logic is TIMSK(0);alias OCIE0     : std_logic is TIMSK(1);alias TOIE1     : std_logic is TIMSK(2);alias OCIE1B    : std_logic is TIMSK(3);alias OCIE1A    : std_logic is TIMSK(4);alias TICIE1    : std_logic is TIMSK(5);alias TOIE2     : std_logic is TIMSK(6);alias OCIE2     : std_logic is TIMSK(7);-- TIFR bitsalias TOV0     : std_logic is TIFR(0);alias OCF0     : std_logic is TIFR(1);alias TOV1     : std_logic is TIFR(2);alias OCF1B    : std_logic is TIFR(3);alias OCF1A    : std_logic is TIFR(4);alias ICF1     : std_logic is TIFR(5);alias TOV2     : std_logic is TIFR(6);alias OCF2     : std_logic is TIFR(7);-- Prescaler1 signalssignal CK8    : std_logic := '0';signal CK64   : std_logic := '0';signal CK256  : std_logic := '0';signal CK1024 : std_logic := '0';signal Pre1Cnt : std_logic_vector(9 downto 0) := (others => '0'); -- Prescaler 1 counter (10-bit)signal EXT1RE : std_logic := '0'; -- Rising edge of external input EXT1 (for TCNT1 only)signal EXT1FE : std_logic := '0'; -- Falling edge of external input EXT1 (for TCNT1 only)signal EXT2RE : std_logic := '0'; -- Rising edge of external input EXT2	(for TCNT2 only)signal EXT2FE : std_logic := '0'; -- Falling edge of external input EXT2 (for TCNT2 only)-- Risign/falling edge detectors	signal EXT1Latched : std_logic := '0';	signal EXT2Latched : std_logic := '0';	-- Prescalers outputs signal TCNT0_En : std_logic := '0'; -- Output of the prescaler 0signal TCNT1_En : std_logic := '0';	-- Output of the prescaler 1signal TCNT2_En : std_logic := '0';	-- Output of the prescaler 1-- Prescaler0 signals	signal PCK0     : std_logic := '0';signal PCK08    : std_logic := '0';signal PCK032   : std_logic := '0';signal PCK064   : std_logic := '0';signal PCK0128  : std_logic := '0';signal PCK0256  : std_logic := '0';signal PCK01024 : std_logic := '0';signal Tosc1RE      : std_logic := '0'; -- Rising edge detector for TOSC1 inputsignal Tosc1Latched : std_logic := '0';signal Pre0Cnt      : std_logic_vector(9 downto 0) := (others => '0'); -- Prescaler 0 counter (10-bit)signal PCK0_Del     : std_logic := '0';-- Timer/counter 0 signalssignal TCNT0_Tmp     : std_logic_vector(7 downto 0) := (others => '0');signal TCNT0_In      : std_logic_vector(7 downto 0) := (others => '0');signal TCNT0_Imm_In  : std_logic_vector(7 downto 0) := (others => '0'); -- Immediate data input signal TCCR0_Tmp     : std_logic_vector(7 downto 0) := (others => '0');signal TCCR0_In      : std_logic_vector(7 downto 0) := (others => '0');signal OCR0_Tmp      : std_logic_vector(7 downto 0) := (others => '0');signal OCR0_In       : std_logic_vector(7 downto 0) := (others => '0');signal TCNT0_Cnt_Dir : std_logic := '0'; -- Count up(0) down (1)signal TCNT0_Clr     : std_logic := '0'; -- Clear (syncronously) TCNT0signal TCNT0_Ld_Imm  : std_logic := '0'; -- Load immediate value (syncronously) TCNT0signal TCNT0_Cmp_Out : std_logic := '0'; -- Output of the comparatorsignal TCNT0_Inc     : std_logic := '0'; -- Increment (not load) took place-- For asynchronous mode onlysignal TCR0UB_Tmp     : std_logic := '0';signal OCR0UB_Tmp     : std_logic := '0';signal TCN0UB_Tmp     : std_logic := '0';-- Timer/counter 2 signalssignal TCNT2_In      : std_logic_vector(7 downto 0) := (others => '0');signal OCR2_Tmp      : std_logic_vector(7 downto 0) := (others => '0');signal TCNT2_Cnt_Dir : std_logic := '0'; -- Count up(0) down (1)signal TCNT2_Clr     : std_logic := '0'; -- Clear (syncronously) TCNT0signal TCNT2_Imm_In  : std_logic_vector(7 downto 0) := (others => '0'); -- Immediate data input signal TCCR2_Tmp     : std_logic_vector(7 downto 0) := (others => '0');signal OCR2_In       : std_logic_vector(7 downto 0) := (others => '0');signal TCNT2_Ld_Imm  : std_logic := '0'; -- Load immediate value (syncronously) TCNT2signal TCNT2_Cmp_Out : std_logic := '0'; -- Output of the comparatorsignal TCNT2_Inc     : std_logic := '0'; -- Increment (not load) took place-- Synchronizer signalssignal EXT1SA  : std_logic := '0';signal EXT1SB  : std_logic := '0'; -- Output of the synchronizer for EXT1signal EXT2SA  : std_logic := '0';signal EXT2SB  : std_logic := '0'; -- Output of the synchronizer for EXT1signal Tosc1SA : std_logic := '0';signal Tosc1SB : std_logic := '0'; -- Output of the synchronizer for Tosc1-- TBD-- Timer/counter 1 signals-- TBD-- Additonal signals (These signals are added in order to emulate the behaviour of the real chip )-- !!! TBD !!!--signal PORTB4_Out : std_logic := '0';--signal PORTB5_Out : std_logic := '0';--signal PORTB6_Out : std_logic := '0';--signal PORTB7_Out : std_logic := '0';begin	-- SynchronizersSyncDFFs:process(cp2,ireset)	begin	 if ireset='0' then      -- Reset  EXT1SA <= '0';    EXT1SB <= '0';     EXT2SA <= '0';     EXT2SB <= '0';     Tosc1SA <= '0';    Tosc1SB <= '0';     elsif cp2='1' and cp2'event then -- Clock    EXT1SA <= EXT1;      EXT1SB <= EXT1SA;       EXT2SA <= EXT2;       EXT2SB <= EXT2SA;       Tosc1SA <= Tosc1;      Tosc1SB <= Tosc1SA; end if;	 end process;