?? dds.flow.rpt
字號:
Flow report for dds
Wed Jun 18 22:04:48 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------+
; Flow Summary ;
+--------------------------+------------------------------------------+
; Flow Status ; Successful - Wed Jun 18 22:04:48 2008 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; dds ;
; Top-level Entity Name ; dds ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C8 ;
; Timing Models ; Final ;
; Met timing requirements ; No ;
; Total logic elements ; 977 / 5,980 ( 16 % ) ;
; Total pins ; 38 / 185 ( 21 % ) ;
; Total virtual pins ; 1 ;
; Total memory bits ; 20,480 / 92,160 ( 22 % ) ;
; DSP block 9-bit elements ; N/A until Partition Merge ;
; Total PLLs ; 1 / 2 ( 50 % ) ;
; Total DLLs ; N/A until Partition Merge ;
+--------------------------+------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 06/18/2008 22:03:20 ;
; Main task ; Compilation ;
; Revision Name ; dds ;
+-------------------+---------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+---------------------------------------------------------------------------------------------+---------------+-------------+------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+---------------------------------------------------------------------------------------------+---------------+-------------+------------------+
; ENABLE_SIGNALTAP ; On ; -- ; -- ; -- ;
; PARTITION_COLOR ; 2147039 ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ;
; SLD_NODE_CREATOR_ID ; 110 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_ENTITY_NAME ; sld_signaltap ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_INFO=805334528 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_POWER_UP_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SEGMENT_SIZE=1024 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_FLOW_USE_GENERATED=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_BITS=11 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_BUFFER_FULL_STOP=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_CURRENT_RESOURCE_WIDTH=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SAMPLE_DEPTH=1024 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_IN_ENABLED=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ADVANCED_TRIGGER_ENTITY=basic,1, ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL_PIPELINE=1 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ENABLE_ADVANCED_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_DATA_BITS=16 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_BITS=16 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK_LENGTH=72 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_CRC_HIWORD=61012 ; -- ; -- ; auto_signaltap_0 ;
; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_CRC_LOWORD=35586 ; -- ; -- ; auto_signaltap_0 ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_palace ;
; USE_SIGNALTAP_FILE ; stp1.stp ; -- ; -- ; -- ;
+------------------------------------+---------------------------------------------------------------------------------------------+---------------+-------------+------------------+
+------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ;
+-------------------------+--------------+-------------------------+
; Analysis & Synthesis ; 00:00:33 ; 1.0 ;
; Fitter ; 00:00:27 ; 1.0 ;
; Assembler ; 00:00:03 ; 1.0 ;
; Classic Timing Analyzer ; 00:00:02 ; 1.0 ;
; Total ; 00:01:05 ; -- ;
+-------------------------+--------------+-------------------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
quartus_fit --read_settings_files=off --write_settings_files=off dds -c dds
quartus_asm --read_settings_files=off --write_settings_files=off dds -c dds
quartus_tan --read_settings_files=off --write_settings_files=off dds -c dds --timing_analysis_only
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