?? top.vwf

?? 高速雙端口RAM的vhdl實(shí)現(xiàn)。包含仿真波形
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		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 48.5;
		LEVEL 0 FOR 891.5;
	}
}

TRANSITION_LIST("In_Wdata[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 84.0;
		LEVEL 1 FOR 24.5;
		LEVEL 0 FOR 891.5;
	}
}

TRANSITION_LIST("In_Wdata[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 24.0;
		LEVEL 0 FOR 916.0;
	}
}

TRANSITION_LIST("In_Wdata[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 72.0;
		LEVEL 1 FOR 12.0;
		LEVEL 0 FOR 12.0;
		LEVEL 1 FOR 12.5;
		LEVEL 0 FOR 891.5;
	}
}

TRANSITION_LIST("In_Wdata[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 48.5;
		LEVEL 0 FOR 891.5;
	}
}

TRANSITION_LIST("In_Wdata[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 84.0;
		LEVEL 1 FOR 24.5;
		LEVEL 0 FOR 891.5;
	}
}

TRANSITION_LIST("In_Wdata[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 24.0;
		LEVEL 0 FOR 916.0;
	}
}

TRANSITION_LIST("In_Wdata[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 72.0;
		LEVEL 1 FOR 12.0;
		LEVEL 0 FOR 12.0;
		LEVEL 1 FOR 12.5;
		LEVEL 0 FOR 891.5;
	}
}

TRANSITION_LIST("In_Wen")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 0 FOR 60.0;
		LEVEL 1 FOR 48.5;
		LEVEL 0 FOR 891.5;
	}
}

TRANSITION_LIST("Out_Rdata[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Out_Rdata[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Out_Rdata[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Out_Rdata[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Out_Rdata[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Out_Rdata[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Out_Rdata[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

TRANSITION_LIST("Out_Rdata[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 1000.0;
	}
}

DISPLAY_LINE
{
	CHANNEL = "In_Raddr";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 0;
	TREE_LEVEL = 0;
	CHILDREN = 1, 2, 3, 4, 5;
}

DISPLAY_LINE
{
	CHANNEL = "In_Raddr[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 1;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "In_Raddr[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 2;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "In_Raddr[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 3;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "In_Raddr[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 4;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "In_Raddr[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 5;
	TREE_LEVEL = 1;
	PARENT = 0;
}

DISPLAY_LINE
{
	CHANNEL = "In_Rclk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 6;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "In_Waddr";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 7;
	TREE_LEVEL = 0;
	CHILDREN = 8, 9, 10, 11, 12;
}

DISPLAY_LINE
{
	CHANNEL = "In_Waddr[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 8;
	TREE_LEVEL = 1;
	PARENT = 7;
}

DISPLAY_LINE
{
	CHANNEL = "In_Waddr[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 9;
	TREE_LEVEL = 1;
	PARENT = 7;
}

DISPLAY_LINE
{
	CHANNEL = "In_Waddr[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 10;
	TREE_LEVEL = 1;
	PARENT = 7;
}

DISPLAY_LINE
{
	CHANNEL = "In_Waddr[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 11;
	TREE_LEVEL = 1;
	PARENT = 7;
}

DISPLAY_LINE
{
	CHANNEL = "In_Waddr[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 12;
	TREE_LEVEL = 1;
	PARENT = 7;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wclk";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 13;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Hexadecimal;
	TREE_INDEX = 14;
	TREE_LEVEL = 0;
	CHILDREN = 15, 16, 17, 18, 19, 20, 21, 22;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 15;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 16;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 17;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 18;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 19;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 20;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 21;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wdata[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 22;
	TREE_LEVEL = 1;
	PARENT = 14;
}

DISPLAY_LINE
{
	CHANNEL = "In_Wen";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 23;
	TREE_LEVEL = 0;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 24;
	TREE_LEVEL = 0;
	CHILDREN = 25, 26, 27, 28, 29, 30, 31, 32;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[7]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 25;
	TREE_LEVEL = 1;
	PARENT = 24;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[6]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 26;
	TREE_LEVEL = 1;
	PARENT = 24;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[5]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 27;
	TREE_LEVEL = 1;
	PARENT = 24;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[4]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 28;
	TREE_LEVEL = 1;
	PARENT = 24;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[3]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 29;
	TREE_LEVEL = 1;
	PARENT = 24;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[2]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 30;
	TREE_LEVEL = 1;
	PARENT = 24;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[1]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 31;
	TREE_LEVEL = 1;
	PARENT = 24;
}

DISPLAY_LINE
{
	CHANNEL = "Out_Rdata[0]";
	EXPAND_STATUS = COLLAPSED;
	RADIX = Binary;
	TREE_INDEX = 32;
	TREE_LEVEL = 1;
	PARENT = 24;
}

TIME_BAR
{
	TIME = 18400;
	MASTER = TRUE;
}
;
上一頁(yè)12
?? 文件大小 297 K
?? 上傳用戶 ccuading
?? 所屬分類 VHDL/FPGA/Verilog
??? 相關(guān)標(biāo)簽

#vhdl #RAM #雙端口 #仿真
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