?? ad0809.vhd
字號:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ad0809 is
port (D: in std_logic_vector(7 downto 0);
CLK,INT,RESET: in std_logic;
CS,RD,WR: out std_logic;
LOCK0 : OUT STD_LOGIC;
DOUT : OUT std_logic_vector(7 downto 0) );
end ad0809;
architecture one of ad0809 is
signal datain : std_logic_vector(7 downto 0);
signal lock : std_logic;
type statetype is(idle,write,swait,read,slock);
signal present_state,next_state: statetype;
begin
P1: process(present_state,next_state,INT)
begin
case present_state is
when idle => CS<='1'; WR<='1'; RD<='1';lock<='0';
next_state<=write;
when write => CS<='1'; WR<='0'; RD<='1';lock<='0';
next_state<=swait;
when swait => CS<='1'; WR<='1'; RD<='1';lock<='0';
if ( INT='0') then
next_state<=read;
else
next_state<=swait;
end if;
when read => CS<='1'; WR<='1'; RD<='0';lock<='0';
next_state<=slock;
when slock => CS<='1'; WR<='1'; RD<='0';lock<='1';
next_state<=idle;
end case;
end process P1;
P2: process(CLK, RESET)
begin
if(RESET='0') then
present_state<=idle;
--datain<="00000000";
elsif(CLK'event and CLK='1') then
present_state<=next_state;
--if(present_state=read) then
--datain<=D;
--end if;
end if;
end process P2;
p3 : process(lock)
begin
if lock = '1' and lock'event then datain <= D;
end if;
end process;
LOCK0 <= lock;
Dout <= datain;
end one;
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