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--D1_present_state.read is ad0809:inst2|present_state.read at LC_X8_Y13_N4
--operation mode is normal

D1_present_state.read_lut_out = !INT & D1_present_state.swait;
D1_present_state.read = DFFEAS(D1_present_state.read_lut_out, GLOBAL(CLK), GLOBAL(CLR), , , , , , );


--D1L15 is ad0809:inst2|RD~0 at LC_X8_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_present_state.slock_qfbk = D1_present_state.slock;
D1L15 = D1_present_state.read # D1_present_state.slock_qfbk;

--D1_present_state.slock is ad0809:inst2|present_state.slock at LC_X8_Y13_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

D1_present_state.slock = DFFEAS(D1L15, GLOBAL(CLK), GLOBAL(CLR), , , D1_present_state.read, , , VCC);


--D1_present_state.write is ad0809:inst2|present_state.write at LC_X8_Y13_N8
--operation mode is normal

D1_present_state.write_lut_out = !D1_present_state.idle;
D1_present_state.write = DFFEAS(D1_present_state.write_lut_out, GLOBAL(CLK), GLOBAL(CLR), , , , , , );


--F1_ram_block1a15 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a15 at M4K_X19_Y14
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a15_PORT_A_data_in = D1_datain[7];
F1_ram_block1a15_PORT_A_data_in_reg = DFFE(F1_ram_block1a15_PORT_A_data_in, F1_ram_block1a15_clock_0, , , F1_ram_block1a15_clock_enable_0);
F1_ram_block1a15_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a15_PORT_A_address_reg = DFFE(F1_ram_block1a15_PORT_A_address, F1_ram_block1a15_clock_0, , , F1_ram_block1a15_clock_enable_0);
F1_ram_block1a15_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a15_PORT_A_write_enable_reg = DFFE(F1_ram_block1a15_PORT_A_write_enable, F1_ram_block1a15_clock_0, , , F1_ram_block1a15_clock_enable_0);
F1_ram_block1a15_clock_0 = GLOBAL(C1L1);
F1_ram_block1a15_clock_enable_0 = G1L6;
F1_ram_block1a15_PORT_A_data_out = MEMORY(F1_ram_block1a15_PORT_A_data_in_reg, , F1_ram_block1a15_PORT_A_address_reg, , F1_ram_block1a15_PORT_A_write_enable_reg, , , , F1_ram_block1a15_clock_0, , F1_ram_block1a15_clock_enable_0, , , );
F1_ram_block1a15 = F1_ram_block1a15_PORT_A_data_out[0];


--F1_ram_block1a23 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a23 at M4K_X19_Y15
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a23_PORT_A_data_in = D1_datain[7];
F1_ram_block1a23_PORT_A_data_in_reg = DFFE(F1_ram_block1a23_PORT_A_data_in, F1_ram_block1a23_clock_0, , , F1_ram_block1a23_clock_enable_0);
F1_ram_block1a23_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a23_PORT_A_address_reg = DFFE(F1_ram_block1a23_PORT_A_address, F1_ram_block1a23_clock_0, , , F1_ram_block1a23_clock_enable_0);
F1_ram_block1a23_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a23_PORT_A_write_enable_reg = DFFE(F1_ram_block1a23_PORT_A_write_enable, F1_ram_block1a23_clock_0, , , F1_ram_block1a23_clock_enable_0);
F1_ram_block1a23_clock_0 = GLOBAL(C1L1);
F1_ram_block1a23_clock_enable_0 = G1L9;
F1_ram_block1a23_PORT_A_data_out = MEMORY(F1_ram_block1a23_PORT_A_data_in_reg, , F1_ram_block1a23_PORT_A_address_reg, , F1_ram_block1a23_PORT_A_write_enable_reg, , , , F1_ram_block1a23_clock_0, , F1_ram_block1a23_clock_enable_0, , , );
F1_ram_block1a23 = F1_ram_block1a23_PORT_A_data_out[0];


--F1_ram_block1a7 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a7 at M4K_X19_Y19
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a7_PORT_A_data_in = D1_datain[7];
F1_ram_block1a7_PORT_A_data_in_reg = DFFE(F1_ram_block1a7_PORT_A_data_in, F1_ram_block1a7_clock_0, , , F1_ram_block1a7_clock_enable_0);
F1_ram_block1a7_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a7_PORT_A_address_reg = DFFE(F1_ram_block1a7_PORT_A_address, F1_ram_block1a7_clock_0, , , F1_ram_block1a7_clock_enable_0);
F1_ram_block1a7_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a7_PORT_A_write_enable_reg = DFFE(F1_ram_block1a7_PORT_A_write_enable, F1_ram_block1a7_clock_0, , , F1_ram_block1a7_clock_enable_0);
F1_ram_block1a7_clock_0 = GLOBAL(C1L1);
F1_ram_block1a7_clock_enable_0 = G1L3;
F1_ram_block1a7_PORT_A_data_out = MEMORY(F1_ram_block1a7_PORT_A_data_in_reg, , F1_ram_block1a7_PORT_A_address_reg, , F1_ram_block1a7_PORT_A_write_enable_reg, , , , F1_ram_block1a7_clock_0, , F1_ram_block1a7_clock_enable_0, , , );
F1_ram_block1a7 = F1_ram_block1a7_PORT_A_data_out[0];


--H1L15 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[7]~352 at LC_X16_Y13_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_address_reg_a[0]_qfbk = F1_address_reg_a[0];
H1L15 = F1_address_reg_a[1] & (F1_ram_block1a23 # F1_address_reg_a[0]_qfbk) # !F1_address_reg_a[1] & (!F1_address_reg_a[0]_qfbk & F1_ram_block1a7);

--F1_address_reg_a[0] is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|address_reg_a[0] at LC_X16_Y13_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_address_reg_a[0] = DFFEAS(H1L15, GLOBAL(C1L1), VCC, , , C1_CQI[12], , , VCC);


--F1_ram_block1a31 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a31 at M4K_X19_Y18
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a31_PORT_A_data_in = D1_datain[7];
F1_ram_block1a31_PORT_A_data_in_reg = DFFE(F1_ram_block1a31_PORT_A_data_in, F1_ram_block1a31_clock_0, , , F1_ram_block1a31_clock_enable_0);
F1_ram_block1a31_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a31_PORT_A_address_reg = DFFE(F1_ram_block1a31_PORT_A_address, F1_ram_block1a31_clock_0, , , F1_ram_block1a31_clock_enable_0);
F1_ram_block1a31_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a31_PORT_A_write_enable_reg = DFFE(F1_ram_block1a31_PORT_A_write_enable, F1_ram_block1a31_clock_0, , , F1_ram_block1a31_clock_enable_0);
F1_ram_block1a31_clock_0 = GLOBAL(C1L1);
F1_ram_block1a31_clock_enable_0 = G1L12;
F1_ram_block1a31_PORT_A_data_out = MEMORY(F1_ram_block1a31_PORT_A_data_in_reg, , F1_ram_block1a31_PORT_A_address_reg, , F1_ram_block1a31_PORT_A_write_enable_reg, , , , F1_ram_block1a31_clock_0, , F1_ram_block1a31_clock_enable_0, , , );
F1_ram_block1a31 = F1_ram_block1a31_PORT_A_data_out[0];


--H1L16 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[7]~353 at LC_X16_Y13_N8
--operation mode is normal

H1L16 = H1L15 & (F1_ram_block1a31 # !F1_address_reg_a[0]) # !H1L15 & (F1_ram_block1a15 & F1_address_reg_a[0]);


--F1_ram_block1a22 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a22 at M4K_X19_Y12
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a22_PORT_A_data_in = D1_datain[6];
F1_ram_block1a22_PORT_A_data_in_reg = DFFE(F1_ram_block1a22_PORT_A_data_in, F1_ram_block1a22_clock_0, , , F1_ram_block1a22_clock_enable_0);
F1_ram_block1a22_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a22_PORT_A_address_reg = DFFE(F1_ram_block1a22_PORT_A_address, F1_ram_block1a22_clock_0, , , F1_ram_block1a22_clock_enable_0);
F1_ram_block1a22_PORT_A_write_enable = G1_w_anode242w[2];
F1_ram_block1a22_PORT_A_write_enable_reg = DFFE(F1_ram_block1a22_PORT_A_write_enable, F1_ram_block1a22_clock_0, , , F1_ram_block1a22_clock_enable_0);
F1_ram_block1a22_clock_0 = GLOBAL(C1L1);
F1_ram_block1a22_clock_enable_0 = G1L9;
F1_ram_block1a22_PORT_A_data_out = MEMORY(F1_ram_block1a22_PORT_A_data_in_reg, , F1_ram_block1a22_PORT_A_address_reg, , F1_ram_block1a22_PORT_A_write_enable_reg, , , , F1_ram_block1a22_clock_0, , F1_ram_block1a22_clock_enable_0, , , );
F1_ram_block1a22 = F1_ram_block1a22_PORT_A_data_out[0];


--F1_ram_block1a14 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a14 at M4K_X19_Y13
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a14_PORT_A_data_in = D1_datain[6];
F1_ram_block1a14_PORT_A_data_in_reg = DFFE(F1_ram_block1a14_PORT_A_data_in, F1_ram_block1a14_clock_0, , , F1_ram_block1a14_clock_enable_0);
F1_ram_block1a14_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a14_PORT_A_address_reg = DFFE(F1_ram_block1a14_PORT_A_address, F1_ram_block1a14_clock_0, , , F1_ram_block1a14_clock_enable_0);
F1_ram_block1a14_PORT_A_write_enable = G1_w_anode234w[2];
F1_ram_block1a14_PORT_A_write_enable_reg = DFFE(F1_ram_block1a14_PORT_A_write_enable, F1_ram_block1a14_clock_0, , , F1_ram_block1a14_clock_enable_0);
F1_ram_block1a14_clock_0 = GLOBAL(C1L1);
F1_ram_block1a14_clock_enable_0 = G1L6;
F1_ram_block1a14_PORT_A_data_out = MEMORY(F1_ram_block1a14_PORT_A_data_in_reg, , F1_ram_block1a14_PORT_A_address_reg, , F1_ram_block1a14_PORT_A_write_enable_reg, , , , F1_ram_block1a14_clock_0, , F1_ram_block1a14_clock_enable_0, , , );
F1_ram_block1a14 = F1_ram_block1a14_PORT_A_data_out[0];


--F1_ram_block1a6 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a6 at M4K_X19_Y11
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a6_PORT_A_data_in = D1_datain[6];
F1_ram_block1a6_PORT_A_data_in_reg = DFFE(F1_ram_block1a6_PORT_A_data_in, F1_ram_block1a6_clock_0, , , F1_ram_block1a6_clock_enable_0);
F1_ram_block1a6_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a6_PORT_A_address_reg = DFFE(F1_ram_block1a6_PORT_A_address, F1_ram_block1a6_clock_0, , , F1_ram_block1a6_clock_enable_0);
F1_ram_block1a6_PORT_A_write_enable = G1_w_anode221w[2];
F1_ram_block1a6_PORT_A_write_enable_reg = DFFE(F1_ram_block1a6_PORT_A_write_enable, F1_ram_block1a6_clock_0, , , F1_ram_block1a6_clock_enable_0);
F1_ram_block1a6_clock_0 = GLOBAL(C1L1);
F1_ram_block1a6_clock_enable_0 = G1L3;
F1_ram_block1a6_PORT_A_data_out = MEMORY(F1_ram_block1a6_PORT_A_data_in_reg, , F1_ram_block1a6_PORT_A_address_reg, , F1_ram_block1a6_PORT_A_write_enable_reg, , , , F1_ram_block1a6_clock_0, , F1_ram_block1a6_clock_enable_0, , , );
F1_ram_block1a6 = F1_ram_block1a6_PORT_A_data_out[0];


--H1L13 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[6]~354 at LC_X16_Y13_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_address_reg_a[1]_qfbk = F1_address_reg_a[1];
H1L13 = F1_address_reg_a[0] & (F1_ram_block1a14 # F1_address_reg_a[1]_qfbk) # !F1_address_reg_a[0] & (!F1_address_reg_a[1]_qfbk & F1_ram_block1a6);

--F1_address_reg_a[1] is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|address_reg_a[1] at LC_X16_Y13_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

F1_address_reg_a[1] = DFFEAS(H1L13, GLOBAL(C1L1), VCC, , , C1_CQI[13], , , VCC);


--F1_ram_block1a30 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a30 at M4K_X19_Y17
--RAM Block Operation Mode: Single Port
--Port A Depth: 4096, Port A Width: 1
--Port A Logical Depth: 16384, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Un-registered
F1_ram_block1a30_PORT_A_data_in = D1_datain[6];
F1_ram_block1a30_PORT_A_data_in_reg = DFFE(F1_ram_block1a30_PORT_A_data_in, F1_ram_block1a30_clock_0, , , F1_ram_block1a30_clock_enable_0);
F1_ram_block1a30_PORT_A_address = BUS(C1_CQI[0], C1_CQI[1], C1_CQI[2], C1_CQI[3], C1_CQI[4], C1_CQI[5], C1_CQI[6], C1_CQI[7], C1_CQI[8], C1_CQI[9], C1_CQI[10], C1_CQI[11]);
F1_ram_block1a30_PORT_A_address_reg = DFFE(F1_ram_block1a30_PORT_A_address, F1_ram_block1a30_clock_0, , , F1_ram_block1a30_clock_enable_0);
F1_ram_block1a30_PORT_A_write_enable = G1_w_anode250w[2];
F1_ram_block1a30_PORT_A_write_enable_reg = DFFE(F1_ram_block1a30_PORT_A_write_enable, F1_ram_block1a30_clock_0, , , F1_ram_block1a30_clock_enable_0);
F1_ram_block1a30_clock_0 = GLOBAL(C1L1);
F1_ram_block1a30_clock_enable_0 = G1L12;
F1_ram_block1a30_PORT_A_data_out = MEMORY(F1_ram_block1a30_PORT_A_data_in_reg, , F1_ram_block1a30_PORT_A_address_reg, , F1_ram_block1a30_PORT_A_write_enable_reg, , , , F1_ram_block1a30_clock_0, , F1_ram_block1a30_clock_enable_0, , , );
F1_ram_block1a30 = F1_ram_block1a30_PORT_A_data_out[0];


--H1L14 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|mux_2bb:mux2|result_node[6]~355 at LC_X16_Y13_N2
--operation mode is normal

H1L14 = F1_address_reg_a[1] & (H1L13 & (F1_ram_block1a30) # !H1L13 & F1_ram_block1a22) # !F1_address_reg_a[1] & (H1L13);


--F1_ram_block1a13 is soundram:inst|altsyncram:altsyncram_component|altsyncram_i041:auto_generated|ram_block1a13 at M4K_X19_Y8
--RAM Block Operation Mode: Single Port