;     -- 0 input functions                    ; 0        ;
;         -- Combinational cells for routing  ; 0        ;
;                                             ;          ;
; Logic elements by mode                      ;          ;
;     -- normal mode                          ; 31       ;
;     -- arithmetic mode                      ; 0        ;
;     -- qfbk mode                            ; 0        ;
;     -- register cascade mode                ; 0        ;
;     -- synchronous clear/load mode          ; 0        ;
;     -- asynchronous clear/load mode         ; 0        ;
;                                             ;          ;
; Total registers                             ; 0        ;
; I/O pins                                    ; 20       ;
; Maximum fan-out node                        ; Index[1] ;
; Maximum fan-out                             ; 16       ;
; Total fan-out                               ; 119      ;
; Average fan-out                             ; 2.33     ;
+---------------------------------------------+----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |ToneTaba                  ; 31 (31)     ; 0            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 20   ; 0            ; 31 (31)      ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |ToneTaba           ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                                ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name                                          ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; CODE[0]$latch                                       ; Mux4                ; yes                    ;
; CODE[1]$latch                                       ; Mux4                ; yes                    ;
; CODE[2]$latch                                       ; Mux4                ; yes                    ;
; HIGH$latch                                          ; Mux4                ; yes                    ;
; Tone[0]$latch                                       ; Mux4                ; yes                    ;
; Tone[1]$latch                                       ; Mux4                ; yes                    ;
; Tone[2]$latch                                       ; Mux4                ; yes                    ;
; Tone[3]$latch                                       ; Mux4                ; yes                    ;
; Tone[4]$latch                                       ; Mux4                ; yes                    ;
; Tone[5]$latch                                       ; Mux4                ; yes                    ;
; Tone[6]$latch                                       ; Mux4                ; yes                    ;
; Tone[7]$latch                                       ; Mux4                ; yes                    ;
; Tone[8]$latch                                       ; Mux4                ; yes                    ;
; Tone[9]$latch                                       ; Mux4                ; yes                    ;
; Tone[10]$latch                                      ; Mux4                ; yes                    ;
; Number of user-specified and inferred latches = 15  ;                     ;                        ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 202 06/20/2006 Service Pack 1 SJ Full Version
    Info: Processing started: Tue Apr 29 15:05:50 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ToneTaba -c ToneTaba
Warning: Using design file ToneTaba.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: ToneTaba-one
    Info: Found entity 1: ToneTaba
Info: Elaborating entity "ToneTaba" for the top level hierarchy
Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable "Tone", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable "CODE", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at ToneTaba.vhd(11): inferring latch(es) for signal or variable "HIGH", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "HIGH"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[0]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[1]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[2]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "CODE[3]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[0]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[1]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[2]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[3]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[4]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[5]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[6]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[7]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[8]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[9]"
Info (10041): Verilog HDL or VHDL info at ToneTaba.vhd(11): inferred latch for "Tone[10]"
Warning: Latch CODE[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch CODE[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch CODE[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[2]
Warning: Latch HIGH$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[1]
Warning: Latch Tone[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[7]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[8]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[3]
Warning: Latch Tone[9]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Latch Tone[10]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal Index[0]
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "CODE[3]" stuck at GND
Info: Implemented 51 device resources after synthesis - the final resource count might be different
    Info: Implemented 4 input pins
    Info: Implemented 16 output pins
    Info: Implemented 31 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 36 warnings
    Info: Processing ended: Tue Apr 29 15:05:52 2008
    Info: Elapsed time: 00:00:02