{ "Info" "ITDB_TSU_RESULT" "HIGH\$latch Index\[1\] Index\[3\] 2.644 ns register " "Info: tsu for register \"HIGH\$latch\" (data pin = \"Index\[1\]\", clock pin = \"Index\[3\]\") is 2.644 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.475 ns + Longest pin register " "Info: + Longest pin to register delay is 7.475 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Index\[1\] 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'Index\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Index[1] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.230 ns) + CELL(0.280 ns) 5.338 ns Mux0~6 2 COMB LC_X1_Y17_N3 1 " "Info: 2: + IC(4.230 ns) + CELL(0.280 ns) = 5.338 ns; Loc. = LC_X1_Y17_N3; Fanout = 1; COMB Node = 'Mux0~6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.510 ns" { Index[1] Mux0~6 } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.857 ns) + CELL(0.280 ns) 7.475 ns HIGH\$latch 3 REG LC_X9_Y2_N7 1 " "Info: 3: + IC(1.857 ns) + CELL(0.280 ns) = 7.475 ns; Loc. = LC_X9_Y2_N7; Fanout = 1; REG Node = 'HIGH\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.137 ns" { Mux0~6 HIGH$latch } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.388 ns ( 18.57 % ) " "Info: Total cell delay = 1.388 ns ( 18.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.087 ns ( 81.43 % ) " "Info: Total interconnect delay = 6.087 ns ( 81.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.475 ns" { Index[1] Mux0~6 HIGH$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.475 ns" { Index[1] Index[1]~out0 Mux0~6 HIGH$latch } { 0.000ns 0.000ns 4.230ns 1.857ns } { 0.000ns 0.828ns 0.280ns 0.280ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.584 ns + " "Info: + Micro setup delay of destination is 0.584 ns" {  } { { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Index\[3\] destination 5.415 ns - Shortest register " "Info: - Shortest clock path from clock \"Index\[3\]\" to destination register is 5.415 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns Index\[3\] 1 CLK PIN_M21 16 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 16; CLK Node = 'Index\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Index[3] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.225 ns) + CELL(0.280 ns) 2.230 ns Mux4~3 2 COMB LC_X1_Y17_N2 15 " "Info: 2: + IC(1.225 ns) + CELL(0.280 ns) = 2.230 ns; Loc. = LC_X1_Y17_N2; Fanout = 15; COMB Node = 'Mux4~3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.505 ns" { Index[3] Mux4~3 } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.110 ns) + CELL(0.075 ns) 5.415 ns HIGH\$latch 3 REG LC_X9_Y2_N7 1 " "Info: 3: + IC(3.110 ns) + CELL(0.075 ns) = 5.415 ns; Loc. = LC_X9_Y2_N7; Fanout = 1; REG Node = 'HIGH\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.185 ns" { Mux4~3 HIGH$latch } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.080 ns ( 19.94 % ) " "Info: Total cell delay = 1.080 ns ( 19.94 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.335 ns ( 80.06 % ) " "Info: Total interconnect delay = 4.335 ns ( 80.06 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.415 ns" { Index[3] Mux4~3 HIGH$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.415 ns" { Index[3] Index[3]~out0 Mux4~3 HIGH$latch } { 0.000ns 0.000ns 1.225ns 3.110ns } { 0.000ns 0.725ns 0.280ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.475 ns" { Index[1] Mux0~6 HIGH$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.475 ns" { Index[1] Index[1]~out0 Mux0~6 HIGH$latch } { 0.000ns 0.000ns 4.230ns 1.857ns } { 0.000ns 0.828ns 0.280ns 0.280ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.415 ns" { Index[3] Mux4~3 HIGH$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.415 ns" { Index[3] Index[3]~out0 Mux4~3 HIGH$latch } { 0.000ns 0.000ns 1.225ns 3.110ns } { 0.000ns 0.725ns 0.280ns 0.075ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Index\[1\] Tone\[9\] Tone\[9\]\$latch 9.801 ns register " "Info: tco from clock \"Index\[1\]\" to destination pin \"Tone\[9\]\" through register \"Tone\[9\]\$latch\" is 9.801 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Index\[1\] source 5.604 ns + Longest register " "Info: + Longest clock path from clock \"Index\[1\]\" to source register is 5.604 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Index\[1\] 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'Index\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Index[1] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.443 ns) + CELL(0.075 ns) 2.346 ns Mux4~3 2 COMB LC_X1_Y17_N2 15 " "Info: 2: + IC(1.443 ns) + CELL(0.075 ns) = 2.346 ns; Loc. = LC_X1_Y17_N2; Fanout = 15; COMB Node = 'Mux4~3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.518 ns" { Index[1] Mux4~3 } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.183 ns) + CELL(0.075 ns) 5.604 ns Tone\[9\]\$latch 3 REG LC_X1_Y12_N9 1 " "Info: 3: + IC(3.183 ns) + CELL(0.075 ns) = 5.604 ns; Loc. = LC_X1_Y12_N9; Fanout = 1; REG Node = 'Tone\[9\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.258 ns" { Mux4~3 Tone[9]$latch } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.978 ns ( 17.45 % ) " "Info: Total cell delay = 0.978 ns ( 17.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.626 ns ( 82.55 % ) " "Info: Total interconnect delay = 4.626 ns ( 82.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.604 ns" { Index[1] Mux4~3 Tone[9]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.604 ns" { Index[1] Index[1]~out0 Mux4~3 Tone[9]$latch } { 0.000ns 0.000ns 1.443ns 3.183ns } { 0.000ns 0.828ns 0.075ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.197 ns + Longest register pin " "Info: + Longest register to pin delay is 4.197 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns Tone\[9\]\$latch 1 REG LC_X1_Y12_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X1_Y12_N9; Fanout = 1; REG Node = 'Tone\[9\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Tone[9]$latch } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.821 ns) + CELL(2.376 ns) 4.197 ns Tone\[9\] 2 PIN PIN_K21 0 " "Info: 2: + IC(1.821 ns) + CELL(2.376 ns) = 4.197 ns; Loc. = PIN_K21; Fanout = 0; PIN Node = 'Tone\[9\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.197 ns" { Tone[9]$latch Tone[9] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.376 ns ( 56.61 % ) " "Info: Total cell delay = 2.376 ns ( 56.61 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.821 ns ( 43.39 % ) " "Info: Total interconnect delay = 1.821 ns ( 43.39 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.197 ns" { Tone[9]$latch Tone[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.197 ns" { Tone[9]$latch Tone[9] } { 0.000ns 1.821ns } { 0.000ns 2.376ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.604 ns" { Index[1] Mux4~3 Tone[9]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.604 ns" { Index[1] Index[1]~out0 Mux4~3 Tone[9]$latch } { 0.000ns 0.000ns 1.443ns 3.183ns } { 0.000ns 0.828ns 0.075ns 0.075ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.197 ns" { Tone[9]$latch Tone[9] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.197 ns" { Tone[9]$latch Tone[9] } { 0.000ns 1.821ns } { 0.000ns 2.376ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "Tone\[9\]\$latch Index\[0\] Index\[1\] 1.060 ns register " "Info: th for register \"Tone\[9\]\$latch\" (data pin = \"Index\[0\]\", clock pin = \"Index\[1\]\") is 1.060 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Index\[1\] destination 5.604 ns + Longest register " "Info: + Longest clock path from clock \"Index\[1\]\" to destination register is 5.604 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns Index\[1\] 1 CLK PIN_M20 16 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 16; CLK Node = 'Index\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Index[1] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.443 ns) + CELL(0.075 ns) 2.346 ns Mux4~3 2 COMB LC_X1_Y17_N2 15 " "Info: 2: + IC(1.443 ns) + CELL(0.075 ns) = 2.346 ns; Loc. = LC_X1_Y17_N2; Fanout = 15; COMB Node = 'Mux4~3'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.518 ns" { Index[1] Mux4~3 } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.183 ns) + CELL(0.075 ns) 5.604 ns Tone\[9\]\$latch 3 REG LC_X1_Y12_N9 1 " "Info: 3: + IC(3.183 ns) + CELL(0.075 ns) = 5.604 ns; Loc. = LC_X1_Y12_N9; Fanout = 1; REG Node = 'Tone\[9\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.258 ns" { Mux4~3 Tone[9]$latch } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.978 ns ( 17.45 % ) " "Info: Total cell delay = 0.978 ns ( 17.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.626 ns ( 82.55 % ) " "Info: Total interconnect delay = 4.626 ns ( 82.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.604 ns" { Index[1] Mux4~3 Tone[9]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.604 ns" { Index[1] Index[1]~out0 Mux4~3 Tone[9]$latch } { 0.000ns 0.000ns 1.443ns 3.183ns } { 0.000ns 0.828ns 0.075ns 0.075ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.544 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.544 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns Index\[0\] 1 CLK PIN_M22 13 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M22; Fanout = 13; CLK Node = 'Index\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Index[0] } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.232 ns) + CELL(0.075 ns) 4.032 ns Mux16~6 2 COMB LC_X1_Y12_N5 1 " "Info: 2: + IC(3.232 ns) + CELL(0.075 ns) = 4.032 ns; Loc. = LC_X1_Y12_N5; Fanout = 1; COMB Node = 'Mux16~6'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.307 ns" { Index[0] Mux16~6 } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.183 ns) 4.544 ns Tone\[9\]\$latch 3 REG LC_X1_Y12_N9 1 " "Info: 3: + IC(0.329 ns) + CELL(0.183 ns) = 4.544 ns; Loc. = LC_X1_Y12_N9; Fanout = 1; REG Node = 'Tone\[9\]\$latch'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.512 ns" { Mux16~6 Tone[9]$latch } "NODE_NAME" } } { "ToneTaba.vhd" "" { Text "D:/ToneTaba/ToneTaba.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.983 ns ( 21.63 % ) " "Info: Total cell delay = 0.983 ns ( 21.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.561 ns ( 78.37 % ) " "Info: Total interconnect delay = 3.561 ns ( 78.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.544 ns" { Index[0] Mux16~6 Tone[9]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.544 ns" { Index[0] Index[0]~out0 Mux16~6 Tone[9]$latch } { 0.000ns 0.000ns 3.232ns 0.329ns } { 0.000ns 0.725ns 0.075ns 0.183ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.604 ns" { Index[1] Mux4~3 Tone[9]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.604 ns" { Index[1] Index[1]~out0 Mux4~3 Tone[9]$latch } { 0.000ns 0.000ns 1.443ns 3.183ns } { 0.000ns 0.828ns 0.075ns 0.075ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.544 ns" { Index[0] Mux16~6 Tone[9]$latch } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.544 ns" { Index[0] Index[0]~out0 Mux16~6 Tone[9]$latch } { 0.000ns 0.000ns 3.232ns 0.329ns } { 0.000ns 0.725ns 0.075ns 0.183ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 18 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Apr 29 15:06:06 2008 " "Info: Processing ended: Tue Apr 29 15:06:06 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}