{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.389 ns register register " "Info: Estimated most critical path is register to register delay of 6.389 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 1 REG LAB_X21_Y10 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X21_Y10; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.750 ns) + CELL(0.590 ns) 1.340 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr~20 2 COMB LAB_X19_Y10 1 " "Info: 2: + IC(0.750 ns) + CELL(0.590 ns) = 1.340 ns; Loc. = LAB_X19_Y10; Fanout = 1; COMB Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr~20'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.340 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~20 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.076 ns) + CELL(0.590 ns) 3.006 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr 3 COMB LAB_X21_Y9 3 " "Info: 3: + IC(1.076 ns) + CELL(0.590 ns) = 3.006 ns; Loc. = LAB_X21_Y9; Fanout = 3; COMB Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_incr_addr'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.666 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~20 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 164 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.555 ns) + CELL(0.432 ns) 4.993 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~96COUT1_105 4 COMB LAB_X19_Y11 2 " "Info: 4: + IC(1.555 ns) + CELL(0.432 ns) = 4.993 ns; Loc. = LAB_X19_Y11; Fanout = 2; COMB Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[0\]~96COUT1_105'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.987 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~96COUT1_105 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.073 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~97COUT1_106 5 COMB LAB_X19_Y11 2 " "Info: 5: + IC(0.000 ns) + CELL(0.080 ns) = 5.073 ns; Loc. = LAB_X19_Y11; Fanout = 2; COMB Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[1\]~97COUT1_106'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~96COUT1_105 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~97COUT1_106 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.153 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~98COUT1_107 6 COMB LAB_X19_Y11 2 " "Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 5.153 ns; Loc. = LAB_X19_Y11; Fanout = 2; COMB Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[2\]~98COUT1_107'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~97COUT1_106 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~98COUT1_107 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.080 ns) 5.233 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~99COUT1 7 COMB LAB_X19_Y11 2 " "Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 5.233 ns; Loc. = LAB_X19_Y11; Fanout = 2; COMB Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[3\]~99COUT1'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.080 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~98COUT1_107 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~99COUT1 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.258 ns) 5.491 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~100 8 COMB LAB_X19_Y11 3 " "Info: 8: + IC(0.000 ns) + CELL(0.258 ns) = 5.491 ns; Loc. = LAB_X19_Y11; Fanout = 3; COMB Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[4\]~100'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.258 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~99COUT1 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~100 } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 6.389 ns NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\] 9 REG LAB_X19_Y11 8 " "Info: 9: + IC(0.000 ns) + CELL(0.898 ns) = 6.389 ns; Loc. = LAB_X19_Y11; Fanout = 8; REG Node = 'NoteTabs:u1\|MUSIC:u1\|altsyncram:altsyncram_component\|altsyncram_k661:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ram_rom_addr_reg\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.898 ns" { NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~100 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } } { "../../altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 379 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.008 ns ( 47.08 % ) " "Info: Total cell delay = 3.008 ns ( 47.08 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.381 ns ( 52.92 % ) " "Info: Total interconnect delay = 3.381 ns ( 52.92 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.389 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~20 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[0]~96COUT1_105 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[1]~97COUT1_106 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[2]~98COUT1_107 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[3]~99COUT1 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[4]~100 NoteTabs:u1|MUSIC:u1|altsyncram:altsyncram_component|altsyncram_k661:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_addr_reg[5] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 2 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y0 x23_y10 " "Info: The peak interconnect region extends from location x12_y0 to location x23_y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr0 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr0" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 390 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr0 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode_usr1 -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode_usr1" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 391 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode_usr1 } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode -- routed using non-global resources" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 392 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "../../altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "D:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "CODE1\[3\] GND " "Info: Pin CODE1\[3\] has GND driving its datain port" {  } { { "Songer.vhd" "" { Text "D:/EDA/Songer/Songer.vhd" 6 -1 0 } } { "d:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "CODE1\[3\]" } } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CODE1[3] } "NODE_NAME" } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { CODE1[3] } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Mon May 19 22:29:46 2008 " "Info: Processing ended: Mon May 19 22:29:46 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Info: Elapsed time: 00:00:08" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/EDA/Songer/Songer.fit.smsg " "Info: Generated suppressed messages file D:/EDA/Songer/Songer.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}