?? cntr_gq7.tdf
字號:
--lpm_counter DEVICE_FAMILY="Cyclone" lpm_direction="UP" lpm_width=11 aclr clock q sclr
--VERSION_BEGIN 4.2 cbx_cycloneii 2004:08:25:19:39:42:SJ cbx_lpm_add_sub 2004:10:25:10:56:48:SJ cbx_lpm_compare 2004:10:18:11:29:46:SJ cbx_lpm_counter 2004:10:25:23:03:40:SJ cbx_lpm_decode 2004:08:15:21:16:20:SJ cbx_mgl 2004:12:23:09:14:54:SJ cbx_stratix 2004:09:23:18:28:34:SJ cbx_stratixii 2004:08:10:15:01:36:SJ VERSION_END
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related netlist (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only
-- to program PLD devices (but not masked PLD devices) from Altera. Any
-- other use of such megafunction design, netlist, support information,
-- device programming or simulation file, or any other related documentation
-- or information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to the
-- intellectual property, including patents, copyrights, trademarks, trade
-- secrets, or maskworks, embodied in any such megafunction design, netlist,
-- support information, device programming or simulation file, or any other
-- related documentation or information provided by Altera or a megafunction
-- partner, remains with Altera, the megafunction partner, or their respective
-- licensors. No other licenses, including any licenses needed under any third
-- party's intellectual property, are provided herein.
FUNCTION cyclone_lcell (aclr, aload, cin, clk, dataa, datab, datac, datad, ena, inverta, regcascin, sclr, sload)
WITH ( cin_used, lut_mask, operation_mode, output_mode, register_cascade_mode, sum_lutc_input, synch_mode)
RETURNS ( combout, cout, regout);
--synthesis_resources = lut 11
SUBDESIGN cntr_gq7
(
aclr : input;
clock : input;
cout : output;
q[10..0] : output;
sclr : input;
)
VARIABLE
counter_cella0 : cyclone_lcell
WITH (
cin_used = "false",
lut_mask = "11AA",
operation_mode = "arithmetic",
synch_mode = "on"
);
counter_cella1 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella2 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella3 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella4 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella5 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella6 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella7 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella8 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella9 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
counter_cella10 : cyclone_lcell
WITH (
cin_used = "true",
lut_mask = "12A0",
operation_mode = "arithmetic",
sum_lutc_input = "cin",
synch_mode = "on"
);
a_val[10..0] : WIRE;
aclr_actual : WIRE;
aset_node : WIRE;
clk_en : NODE;
data[10..0] : NODE;
s_val[10..0] : WIRE;
safe_q[10..0] : WIRE;
sload : NODE;
sset_node : WIRE;
time_to_clear : WIRE;
updownDir : WIRE;
BEGIN
counter_cella[10..0].aclr = aclr_actual;
counter_cella[10..0].aload = B"00000000000";
counter_cella[1].cin = counter_cella[0].cout;
counter_cella[2].cin = counter_cella[1].cout;
counter_cella[3].cin = counter_cella[2].cout;
counter_cella[4].cin = counter_cella[3].cout;
counter_cella[5].cin = counter_cella[4].cout;
counter_cella[6].cin = counter_cella[5].cout;
counter_cella[7].cin = counter_cella[6].cout;
counter_cella[8].cin = counter_cella[7].cout;
counter_cella[9].cin = counter_cella[8].cout;
counter_cella[10].cin = counter_cella[9].cout;
counter_cella[10..0].clk = clock;
counter_cella[10..0].dataa = safe_q[];
counter_cella[10..0].datab = B"00000000000";
counter_cella[10..0].datac = data[];
counter_cella[10..0].ena = clk_en;
counter_cella[10..0].sclr = sclr;
counter_cella[10..0].sload = sload;
a_val[] = B"11111111111";
aclr_actual = aclr;
aset_node = B"0";
clk_en = VCC;
cout = counter_cella[10].cout;
data[] = GND;
q[] = safe_q[];
s_val[] = B"11111111111";
safe_q[] = counter_cella[10..0].regout;
sload = GND;
sset_node = B"0";
time_to_clear = B"0";
updownDir = B"1";
END;
--VALID FILE
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