?? waveform1.vwf

?? FPGA的SRAM存儲器的控制程序
?? VWF
?? 第 1 頁 / 共 4 頁
字號:
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.
*/

HEADER
{
	VERSION = 1;
	TIME_UNIT = ns;
	DATA_OFFSET = 0.0;
	DATA_DURATION = 1000.0;
	SIMULATION_TIME = 0.0;
	GRID_PHASE = 0.0;
	GRID_PERIOD = 10.0;
	GRID_DUTY_CYCLE = 50;
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 18;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[17]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[16]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_ADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_CE_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 16;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_DQ";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_LB_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_OE_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_UB_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|SRAM_WE_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 18;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[17]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[16]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iADDR";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 2;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iBE_N";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iCE_N")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iCLK")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 16;
	LSB_INDEX = 0;
	DIRECTION = BURIED;
	PARENT = "";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = BURIED;
	PARENT = "SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA";
}

SIGNAL("SRAM_16Bit_512K:the_SRAM_16Bit_512K|iDATA[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
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?? 文件大小 652 K
?? 上傳用戶 qingriwanxia
?? 所屬分類 VHDL/FPGA/Verilog
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#FPGA #SRAM #存儲器 #控制
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?? waveform1.vwf

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