?? sram_16bit_512k.xml
字號:
<interfaceDefinition version='1.1' language='verilog' kind='module' name='SRAM_16Bit_512K'>
<portList>
<port name='oDATA' direction='output' type='[15:0]' />
<port name='iDATA' direction='input' type='[15:0]' />
<port name='iADDR' direction='input' type='[17:0]' />
<port name='iWE_N' direction='input' type='' />
<port name='iOE_N' direction='input' type='' />
<port name='iCE_N' direction='input' type='' />
<port name='iCLK' direction='input' type='' />
<port name='iBE_N' direction='input' type='[1:0]' />
<port name='SRAM_DQ' direction='inout' type='[15:0]' />
<port name='SRAM_ADDR' direction='output' type='[17:0]' />
<port name='SRAM_UB_N' direction='output' type='' />
<port name='SRAM_LB_N' direction='output' type='' />
<port name='SRAM_WE_N' direction='output' type='' />
<port name='SRAM_CE_N' direction='output' type='' />
<port name='SRAM_OE_N' direction='output' type='' />
</portList>
</interfaceDefinition>
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