Warning: Node "OTG_ADDR[1]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_CS_N" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DACK0_N" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DACK1_N" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[0]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[10]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[11]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[12]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[13]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[14]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[15]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[1]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[2]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[3]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[4]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[5]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[6]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[7]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[8]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DATA[9]" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DREQ0" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_DREQ1" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_FSPEED" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_INT0" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_INT1" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_LSPEED" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_RD_N" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_RST_N" is assigned to location or region, but does not exist in design
    Warning: Node "OTG_WR_N" is assigned to location or region, but does not exist in design
    Warning: Node "PS2_CLK" is assigned to location or region, but does not exist in design
    Warning: Node "PS2_DAT" is assigned to location or region, but does not exist in design
    Warning: Node "SD_CLK" is assigned to location or region, but does not exist in design
    Warning: Node "SD_CMD" is assigned to location or region, but does not exist in design
    Warning: Node "SD_DAT" is assigned to location or region, but does not exist in design
    Warning: Node "SD_DAT3" is assigned to location or region, but does not exist in design
    Warning: Node "TCK" is assigned to location or region, but does not exist in design
    Warning: Node "TCS" is assigned to location or region, but does not exist in design
    Warning: Node "TDI" is assigned to location or region, but does not exist in design
    Warning: Node "TDO" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[0]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[1]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[2]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[3]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[4]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[5]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[6]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_DATA[7]" is assigned to location or region, but does not exist in design
    Warning: Node "TD_HS" is assigned to location or region, but does not exist in design
    Warning: Node "TD_RESET" is assigned to location or region, but does not exist in design
    Warning: Node "TD_VS" is assigned to location or region, but does not exist in design
    Warning: Node "UART_RXD" is assigned to location or region, but does not exist in design
    Warning: Node "UART_TXD" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_BLANK" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[0]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[1]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[2]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[3]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[4]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[5]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[6]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[7]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[8]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_B[9]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_CLK" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[0]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[1]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[2]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[3]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[4]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[5]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[6]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[7]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[8]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_G[9]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_HS" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[0]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[1]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[2]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[3]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[4]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[5]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[6]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[7]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[8]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_R[9]" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_SYNC" is assigned to location or region, but does not exist in design
    Warning: Node "VGA_VS" is assigned to location or region, but does not exist in design
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is register to register delay of 3.135 ns
    Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X14_Y2; Fanout = 3; REG Node = 'Reset_Delay:r0|Cont[7]'
    Info: 2: + IC(0.473 ns) + CELL(0.150 ns) = 0.623 ns; Loc. = LAB_X14_Y2; Fanout = 1; COMB Node = 'Reset_Delay:r0|Equal0~192'
    Info: 3: + IC(0.415 ns) + CELL(0.150 ns) = 1.188 ns; Loc. = LAB_X14_Y2; Fanout = 1; COMB Node = 'Reset_Delay:r0|Equal0~193'
    Info: 4: + IC(0.127 ns) + CELL(0.438 ns) = 1.753 ns; Loc. = LAB_X14_Y2; Fanout = 21; COMB Node = 'Reset_Delay:r0|Equal0~197'
    Info: 5: + IC(0.722 ns) + CELL(0.660 ns) = 3.135 ns; Loc. = LAB_X14_Y1; Fanout = 3; REG Node = 'Reset_Delay:r0|Cont[10]'
    Info: Total cell delay = 1.398 ns ( 44.59 % )
    Info: Total interconnect delay = 1.737 ns ( 55.41 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 2%
    Info: The peak interconnect region extends from location X11_Y0 to location X21_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
    Info: Optimizations that may affect the design's routability were skipped
    Info: Optimizations that may affect the design's timing were skipped
Info: Started post-fitting delay annotation
Warning: Found 93 output pins without output pin load capacitance assignment
    Info: Pin "SRAM_DQ[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[7]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[8]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[9]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[10]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[11]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[12]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[13]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[14]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis
    Info: Pin "SRAM_DQ[15]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis