|SRAMtest
CLOCK_50 => CLOCK_50~0.IN2
SW[0] => iDATA~31.DATAB
SW[0] => LEDG[0].DATAIN
SW[1] => iDATA~30.DATAB
SW[1] => LEDG[1].DATAIN
SW[2] => iDATA~29.DATAB
SW[2] => LEDG[2].DATAIN
SW[3] => iDATA~28.DATAB
SW[3] => LEDG[3].DATAIN
SW[4] => iDATA~27.DATAB
SW[4] => LEDG[4].DATAIN
SW[5] => iDATA~26.DATAB
SW[5] => LEDG[5].DATAIN
SW[6] => iDATA~25.DATAB
SW[6] => LEDG[6].DATAIN
SW[7] => iDATA~24.DATAB
SW[7] => LEDG[7].DATAIN
SW[8] => iADDR~35.DATAB
SW[8] => Selector18.IN2
SW[8] => LEDR[8].DATAIN
SW[9] => iADDR~34.DATAB
SW[9] => Selector17.IN2
SW[9] => LEDR[9].DATAIN
SW[10] => iADDR~33.DATAB
SW[10] => Selector16.IN2
SW[10] => LEDR[10].DATAIN
SW[11] => iADDR~32.DATAB
SW[11] => Selector15.IN2
SW[11] => LEDR[11].DATAIN
SW[12] => iADDR~31.DATAB
SW[12] => Selector14.IN2
SW[12] => LEDR[12].DATAIN
SW[13] => iADDR~30.DATAB
SW[13] => Selector13.IN2
SW[13] => LEDR[13].DATAIN
SW[14] => iADDR~29.DATAB
SW[14] => Selector12.IN2
SW[14] => LEDR[14].DATAIN
SW[15] => iADDR~28.DATAB
SW[15] => Selector11.IN2
SW[15] => LEDR[15].DATAIN
SW[16] => iADDR~27.DATAB
SW[16] => Selector10.IN2
SW[16] => LEDR[16].DATAIN
SW[17] => iADDR~26.DATAB
SW[17] => Selector9.IN2
SW[17] => LEDR[17].DATAIN
LEDR[0] <= <GND>
LEDR[1] <= <GND>
LEDR[2] <= <GND>
LEDR[3] <= <GND>
LEDR[4] <= <GND>
LEDR[5] <= <GND>
LEDR[6] <= <GND>
LEDR[7] <= <GND>
LEDR[8] <= SW[8].DB_MAX_OUTPUT_PORT_TYPE
LEDR[9] <= SW[9].DB_MAX_OUTPUT_PORT_TYPE
LEDR[10] <= SW[10].DB_MAX_OUTPUT_PORT_TYPE
LEDR[11] <= SW[11].DB_MAX_OUTPUT_PORT_TYPE
LEDR[12] <= SW[12].DB_MAX_OUTPUT_PORT_TYPE
LEDR[13] <= SW[13].DB_MAX_OUTPUT_PORT_TYPE
LEDR[14] <= SW[14].DB_MAX_OUTPUT_PORT_TYPE
LEDR[15] <= SW[15].DB_MAX_OUTPUT_PORT_TYPE
LEDR[16] <= SW[16].DB_MAX_OUTPUT_PORT_TYPE
LEDR[17] <= SW[17].DB_MAX_OUTPUT_PORT_TYPE
LEDG[0] <= SW[0].DB_MAX_OUTPUT_PORT_TYPE
LEDG[1] <= SW[1].DB_MAX_OUTPUT_PORT_TYPE
LEDG[2] <= SW[2].DB_MAX_OUTPUT_PORT_TYPE
LEDG[3] <= SW[3].DB_MAX_OUTPUT_PORT_TYPE
LEDG[4] <= SW[4].DB_MAX_OUTPUT_PORT_TYPE
LEDG[5] <= SW[5].DB_MAX_OUTPUT_PORT_TYPE
LEDG[6] <= SW[6].DB_MAX_OUTPUT_PORT_TYPE
LEDG[7] <= SW[7].DB_MAX_OUTPUT_PORT_TYPE
KEY[0] => Selector35.IN3
KEY[0] => iWE_N~0.OUTPUTSELECT
KEY[0] => iADDR~18.OUTPUTSELECT
KEY[0] => iADDR~19.OUTPUTSELECT
KEY[0] => iADDR~20.OUTPUTSELECT
KEY[0] => iADDR~21.OUTPUTSELECT
KEY[0] => iADDR~22.OUTPUTSELECT
KEY[0] => iADDR~23.OUTPUTSELECT
KEY[0] => iADDR~24.OUTPUTSELECT
KEY[0] => iADDR~25.OUTPUTSELECT
KEY[0] => iADDR~26.OUTPUTSELECT
KEY[0] => iADDR~27.OUTPUTSELECT
KEY[0] => iADDR~28.OUTPUTSELECT
KEY[0] => iADDR~29.OUTPUTSELECT
KEY[0] => iADDR~30.OUTPUTSELECT
KEY[0] => iADDR~31.OUTPUTSELECT
KEY[0] => iADDR~32.OUTPUTSELECT
KEY[0] => iADDR~33.OUTPUTSELECT
KEY[0] => iADDR~34.OUTPUTSELECT
KEY[0] => iADDR~35.OUTPUTSELECT
KEY[0] => iDATA~16.OUTPUTSELECT
KEY[0] => iDATA~17.OUTPUTSELECT
KEY[0] => iDATA~18.OUTPUTSELECT
KEY[0] => iDATA~19.OUTPUTSELECT
KEY[0] => iDATA~20.OUTPUTSELECT
KEY[0] => iDATA~21.OUTPUTSELECT
KEY[0] => iDATA~22.OUTPUTSELECT
KEY[0] => iDATA~23.OUTPUTSELECT
KEY[0] => iDATA~24.OUTPUTSELECT
KEY[0] => iDATA~25.OUTPUTSELECT
KEY[0] => iDATA~26.OUTPUTSELECT
KEY[0] => iDATA~27.OUTPUTSELECT
KEY[0] => iDATA~28.OUTPUTSELECT
KEY[0] => iDATA~29.OUTPUTSELECT
KEY[0] => iDATA~30.OUTPUTSELECT
KEY[0] => iDATA~31.OUTPUTSELECT
KEY[0] => temp_DATA~16.OUTPUTSELECT
KEY[0] => temp_DATA~17.OUTPUTSELECT
KEY[0] => temp_DATA~18.OUTPUTSELECT
KEY[0] => temp_DATA~19.OUTPUTSELECT
KEY[0] => temp_DATA~20.OUTPUTSELECT
KEY[0] => temp_DATA~21.OUTPUTSELECT
KEY[0] => temp_DATA~22.OUTPUTSELECT
KEY[0] => temp_DATA~23.OUTPUTSELECT
KEY[0] => temp_DATA~24.OUTPUTSELECT
KEY[0] => temp_DATA~25.OUTPUTSELECT
KEY[0] => temp_DATA~26.OUTPUTSELECT
KEY[0] => temp_DATA~27.OUTPUTSELECT
KEY[0] => temp_DATA~28.OUTPUTSELECT
KEY[0] => temp_DATA~29.OUTPUTSELECT
KEY[0] => temp_DATA~30.OUTPUTSELECT
KEY[0] => temp_DATA~31.OUTPUTSELECT
KEY[0] => Selector36.IN1
KEY[1] => ~NO_FANOUT~
KEY[2] => ~NO_FANOUT~
KEY[3] => ~NO_FANOUT~
HEX0[0] <= SEG7_LUT_4:seg_4.oSEG0
HEX0[1] <= SEG7_LUT_4:seg_4.oSEG0
HEX0[2] <= SEG7_LUT_4:seg_4.oSEG0
HEX0[3] <= SEG7_LUT_4:seg_4.oSEG0
HEX0[4] <= SEG7_LUT_4:seg_4.oSEG0
HEX0[5] <= SEG7_LUT_4:seg_4.oSEG0
HEX0[6] <= SEG7_LUT_4:seg_4.oSEG0
HEX1[0] <= SEG7_LUT_4:seg_4.oSEG1
HEX1[1] <= SEG7_LUT_4:seg_4.oSEG1
HEX1[2] <= SEG7_LUT_4:seg_4.oSEG1
HEX1[3] <= SEG7_LUT_4:seg_4.oSEG1
HEX1[4] <= SEG7_LUT_4:seg_4.oSEG1
HEX1[5] <= SEG7_LUT_4:seg_4.oSEG1
HEX1[6] <= SEG7_LUT_4:seg_4.oSEG1
HEX2[0] <= SEG7_LUT_4:seg_4.oSEG2
HEX2[1] <= SEG7_LUT_4:seg_4.oSEG2
HEX2[2] <= SEG7_LUT_4:seg_4.oSEG2
HEX2[3] <= SEG7_LUT_4:seg_4.oSEG2
HEX2[4] <= SEG7_LUT_4:seg_4.oSEG2
HEX2[5] <= SEG7_LUT_4:seg_4.oSEG2
HEX2[6] <= SEG7_LUT_4:seg_4.oSEG2
HEX3[0] <= SEG7_LUT_4:seg_4.oSEG3
HEX3[1] <= SEG7_LUT_4:seg_4.oSEG3
HEX3[2] <= SEG7_LUT_4:seg_4.oSEG3
HEX3[3] <= SEG7_LUT_4:seg_4.oSEG3
HEX3[4] <= SEG7_LUT_4:seg_4.oSEG3
HEX3[5] <= SEG7_LUT_4:seg_4.oSEG3
HEX3[6] <= SEG7_LUT_4:seg_4.oSEG3
SRAM_ADDR[0] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[1] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[2] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[3] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[4] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[5] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[6] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[7] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[8] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[9] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[10] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[11] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[12] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[13] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[14] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[15] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[16] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_ADDR[17] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_ADDR
SRAM_UB_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_UB_N
SRAM_LB_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_LB_N
SRAM_WE_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_WE_N
SRAM_CE_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_CE_N
SRAM_OE_N <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_OE_N
SRAM_DQ[0] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[1] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[2] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[3] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[4] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[5] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[6] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[7] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[8] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[9] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[10] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[11] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[12] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[13] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[14] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ
SRAM_DQ[15] <= SRAM_16Bit_512K:the_SRAM_16Bit_512K.SRAM_DQ


|SRAMtest|Reset_Delay:r0
iCLK => Cont[18].CLK
iCLK => Cont[17].CLK
iCLK => Cont[16].CLK
iCLK => Cont[15].CLK
iCLK => Cont[14].CLK
iCLK => Cont[13].CLK
iCLK => Cont[12].CLK
iCLK => Cont[11].CLK
iCLK => Cont[10].CLK
iCLK => Cont[9].CLK
iCLK => Cont[8].CLK
iCLK => Cont[7].CLK
iCLK => Cont[6].CLK
iCLK => Cont[5].CLK
iCLK => Cont[4].CLK
iCLK => Cont[3].CLK
iCLK => Cont[2].CLK
iCLK => Cont[1].CLK
iCLK => Cont[0].CLK
iCLK => oRESET~reg0.CLK
iCLK => Cont[19].CLK
oRESET <= oRESET~reg0.DB_MAX_OUTPUT_PORT_TYPE


|SRAMtest|SRAM_16Bit_512K:the_SRAM_16Bit_512K
oDATA[0] <= oDATA~15.DB_MAX_OUTPUT_PORT_TYPE
oDATA[1] <= oDATA~14.DB_MAX_OUTPUT_PORT_TYPE
oDATA[2] <= oDATA~13.DB_MAX_OUTPUT_PORT_TYPE
oDATA[3] <= oDATA~12.DB_MAX_OUTPUT_PORT_TYPE
oDATA[4] <= oDATA~11.DB_MAX_OUTPUT_PORT_TYPE
oDATA[5] <= oDATA~10.DB_MAX_OUTPUT_PORT_TYPE
oDATA[6] <= oDATA~9.DB_MAX_OUTPUT_PORT_TYPE
oDATA[7] <= oDATA~8.DB_MAX_OUTPUT_PORT_TYPE
oDATA[8] <= oDATA~7.DB_MAX_OUTPUT_PORT_TYPE
oDATA[9] <= oDATA~6.DB_MAX_OUTPUT_PORT_TYPE
oDATA[10] <= oDATA~5.DB_MAX_OUTPUT_PORT_TYPE
oDATA[11] <= oDATA~4.DB_MAX_OUTPUT_PORT_TYPE