oDATA[12] <= oDATA~3.DB_MAX_OUTPUT_PORT_TYPE
oDATA[13] <= oDATA~2.DB_MAX_OUTPUT_PORT_TYPE
oDATA[14] <= oDATA~1.DB_MAX_OUTPUT_PORT_TYPE
oDATA[15] <= oDATA~0.DB_MAX_OUTPUT_PORT_TYPE
iDATA[0] => SRAM_DQ~31.DATAIN
iDATA[1] => SRAM_DQ~30.DATAIN
iDATA[2] => SRAM_DQ~29.DATAIN
iDATA[3] => SRAM_DQ~28.DATAIN
iDATA[4] => SRAM_DQ~27.DATAIN
iDATA[5] => SRAM_DQ~26.DATAIN
iDATA[6] => SRAM_DQ~25.DATAIN
iDATA[7] => SRAM_DQ~24.DATAIN
iDATA[8] => SRAM_DQ~23.DATAIN
iDATA[9] => SRAM_DQ~22.DATAIN
iDATA[10] => SRAM_DQ~21.DATAIN
iDATA[11] => SRAM_DQ~20.DATAIN
iDATA[12] => SRAM_DQ~19.DATAIN
iDATA[13] => SRAM_DQ~18.DATAIN
iDATA[14] => SRAM_DQ~17.DATAIN
iDATA[15] => SRAM_DQ~16.DATAIN
iADDR[0] => SRAM_ADDR[0].DATAIN
iADDR[1] => SRAM_ADDR[1].DATAIN
iADDR[2] => SRAM_ADDR[2].DATAIN
iADDR[3] => SRAM_ADDR[3].DATAIN
iADDR[4] => SRAM_ADDR[4].DATAIN
iADDR[5] => SRAM_ADDR[5].DATAIN
iADDR[6] => SRAM_ADDR[6].DATAIN
iADDR[7] => SRAM_ADDR[7].DATAIN
iADDR[8] => SRAM_ADDR[8].DATAIN
iADDR[9] => SRAM_ADDR[9].DATAIN
iADDR[10] => SRAM_ADDR[10].DATAIN
iADDR[11] => SRAM_ADDR[11].DATAIN
iADDR[12] => SRAM_ADDR[12].DATAIN
iADDR[13] => SRAM_ADDR[13].DATAIN
iADDR[14] => SRAM_ADDR[14].DATAIN
iADDR[15] => SRAM_ADDR[15].DATAIN
iADDR[16] => SRAM_ADDR[16].DATAIN
iADDR[17] => SRAM_ADDR[17].DATAIN
iWE_N => SRAM_WE_N.DATAIN
iWE_N => SRAM_DQ~16.OE
iWE_N => SRAM_DQ~17.OE
iWE_N => SRAM_DQ~18.OE
iWE_N => SRAM_DQ~19.OE
iWE_N => SRAM_DQ~20.OE
iWE_N => SRAM_DQ~21.OE
iWE_N => SRAM_DQ~22.OE
iWE_N => SRAM_DQ~23.OE
iWE_N => SRAM_DQ~24.OE
iWE_N => SRAM_DQ~25.OE
iWE_N => SRAM_DQ~26.OE
iWE_N => SRAM_DQ~27.OE
iWE_N => SRAM_DQ~28.OE
iWE_N => SRAM_DQ~29.OE
iWE_N => SRAM_DQ~30.OE
iWE_N => SRAM_DQ~31.OE
iOE_N => SRAM_OE_N.DATAIN
iCE_N => SRAM_CE_N.DATAIN
iCLK => ~NO_FANOUT~
iBE_N[0] => SRAM_LB_N.DATAIN
iBE_N[1] => SRAM_UB_N.DATAIN
SRAM_DQ[0] <= SRAM_DQ~31
SRAM_DQ[1] <= SRAM_DQ~30
SRAM_DQ[2] <= SRAM_DQ~29
SRAM_DQ[3] <= SRAM_DQ~28
SRAM_DQ[4] <= SRAM_DQ~27
SRAM_DQ[5] <= SRAM_DQ~26
SRAM_DQ[6] <= SRAM_DQ~25
SRAM_DQ[7] <= SRAM_DQ~24
SRAM_DQ[8] <= SRAM_DQ~23
SRAM_DQ[9] <= SRAM_DQ~22
SRAM_DQ[10] <= SRAM_DQ~21
SRAM_DQ[11] <= SRAM_DQ~20
SRAM_DQ[12] <= SRAM_DQ~19
SRAM_DQ[13] <= SRAM_DQ~18
SRAM_DQ[14] <= SRAM_DQ~17
SRAM_DQ[15] <= SRAM_DQ~16
SRAM_ADDR[0] <= iADDR[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[1] <= iADDR[1].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[2] <= iADDR[2].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[3] <= iADDR[3].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[4] <= iADDR[4].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[5] <= iADDR[5].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[6] <= iADDR[6].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[7] <= iADDR[7].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[8] <= iADDR[8].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[9] <= iADDR[9].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[10] <= iADDR[10].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[11] <= iADDR[11].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[12] <= iADDR[12].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[13] <= iADDR[13].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[14] <= iADDR[14].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[15] <= iADDR[15].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[16] <= iADDR[16].DB_MAX_OUTPUT_PORT_TYPE
SRAM_ADDR[17] <= iADDR[17].DB_MAX_OUTPUT_PORT_TYPE
SRAM_UB_N <= iBE_N[1].DB_MAX_OUTPUT_PORT_TYPE
SRAM_LB_N <= iBE_N[0].DB_MAX_OUTPUT_PORT_TYPE
SRAM_WE_N <= iWE_N.DB_MAX_OUTPUT_PORT_TYPE
SRAM_CE_N <= iCE_N.DB_MAX_OUTPUT_PORT_TYPE
SRAM_OE_N <= iOE_N.DB_MAX_OUTPUT_PORT_TYPE


|SRAMtest|SEG7_LUT_4:seg_4
oSEG0[0] <= SEG7_LUT:u0.port0
oSEG0[1] <= SEG7_LUT:u0.port0
oSEG0[2] <= SEG7_LUT:u0.port0
oSEG0[3] <= SEG7_LUT:u0.port0
oSEG0[4] <= SEG7_LUT:u0.port0
oSEG0[5] <= SEG7_LUT:u0.port0
oSEG0[6] <= SEG7_LUT:u0.port0
oSEG1[0] <= SEG7_LUT:u1.port0
oSEG1[1] <= SEG7_LUT:u1.port0
oSEG1[2] <= SEG7_LUT:u1.port0
oSEG1[3] <= SEG7_LUT:u1.port0
oSEG1[4] <= SEG7_LUT:u1.port0
oSEG1[5] <= SEG7_LUT:u1.port0
oSEG1[6] <= SEG7_LUT:u1.port0
oSEG2[0] <= SEG7_LUT:u2.port0
oSEG2[1] <= SEG7_LUT:u2.port0
oSEG2[2] <= SEG7_LUT:u2.port0
oSEG2[3] <= SEG7_LUT:u2.port0
oSEG2[4] <= SEG7_LUT:u2.port0
oSEG2[5] <= SEG7_LUT:u2.port0
oSEG2[6] <= SEG7_LUT:u2.port0
oSEG3[0] <= SEG7_LUT:u3.port0
oSEG3[1] <= SEG7_LUT:u3.port0
oSEG3[2] <= SEG7_LUT:u3.port0
oSEG3[3] <= SEG7_LUT:u3.port0
oSEG3[4] <= SEG7_LUT:u3.port0
oSEG3[5] <= SEG7_LUT:u3.port0
oSEG3[6] <= SEG7_LUT:u3.port0
iDIG[0] => temp_DIG[0].DATAIN
iDIG[1] => temp_DIG[1].DATAIN
iDIG[2] => temp_DIG[2].DATAIN
iDIG[3] => temp_DIG[3].DATAIN
iDIG[4] => temp_DIG[4].DATAIN
iDIG[5] => temp_DIG[5].DATAIN
iDIG[6] => temp_DIG[6].DATAIN
iDIG[7] => temp_DIG[7].DATAIN
iDIG[8] => temp_DIG[8].DATAIN
iDIG[9] => temp_DIG[9].DATAIN
iDIG[10] => temp_DIG[10].DATAIN
iDIG[11] => temp_DIG[11].DATAIN
iDIG[12] => temp_DIG[12].DATAIN
iDIG[13] => temp_DIG[13].DATAIN
iDIG[14] => temp_DIG[14].DATAIN
iDIG[15] => temp_DIG[15].DATAIN
iRESET => temp_DIG[14].ACLR
iRESET => temp_DIG[13].ACLR
iRESET => temp_DIG[12].ACLR
iRESET => temp_DIG[11].ACLR
iRESET => temp_DIG[10].ACLR
iRESET => temp_DIG[9].ACLR
iRESET => temp_DIG[8].ACLR
iRESET => temp_DIG[7].ACLR
iRESET => temp_DIG[6].ACLR
iRESET => temp_DIG[5].ACLR
iRESET => temp_DIG[4].ACLR
iRESET => temp_DIG[3].ACLR
iRESET => temp_DIG[2].ACLR
iRESET => temp_DIG[1].ACLR
iRESET => temp_DIG[0].ACLR
iRESET => temp_DIG[15].ACLR
iCLK => temp_DIG[14].CLK
iCLK => temp_DIG[13].CLK
iCLK => temp_DIG[12].CLK
iCLK => temp_DIG[11].CLK
iCLK => temp_DIG[10].CLK
iCLK => temp_DIG[9].CLK
iCLK => temp_DIG[8].CLK
iCLK => temp_DIG[7].CLK
iCLK => temp_DIG[6].CLK
iCLK => temp_DIG[5].CLK
iCLK => temp_DIG[4].CLK
iCLK => temp_DIG[3].CLK
iCLK => temp_DIG[2].CLK
iCLK => temp_DIG[1].CLK
iCLK => temp_DIG[0].CLK
iCLK => temp_DIG[15].CLK


|SRAMtest|SEG7_LUT_4:seg_4|SEG7_LUT:u0
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|SRAMtest|SEG7_LUT_4:seg_4|SEG7_LUT:u1
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|SRAMtest|SEG7_LUT_4:seg_4|SEG7_LUT:u2
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0


|SRAMtest|SEG7_LUT_4:seg_4|SEG7_LUT:u3
oSEG[0] <= WideOr6.DB_MAX_OUTPUT_PORT_TYPE
oSEG[1] <= WideOr5.DB_MAX_OUTPUT_PORT_TYPE
oSEG[2] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
oSEG[3] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
oSEG[4] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
oSEG[5] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
oSEG[6] <= WideOr0.DB_MAX_OUTPUT_PORT_TYPE
iDIG[0] => Decoder0.IN3
iDIG[1] => Decoder0.IN2
iDIG[2] => Decoder0.IN1
iDIG[3] => Decoder0.IN0