{ "Info" "ITDB_TH_RESULT" "iDATA\[5\] SW\[5\] CLOCK_50 0.318 ns register " "Info: th for register \"iDATA\[5\]\" (data pin = \"SW\[5\]\", clock pin = \"CLOCK_50\") is 0.318 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLOCK_50 destination 2.693 ns + Longest register " "Info: + Longest clock path from clock \"CLOCK_50\" to destination register is 2.693 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns CLOCK_50 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'CLOCK_50'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns CLOCK_50~clkctrl 2 COMB CLKCTRL_G2 77 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 77; COMB Node = 'CLOCK_50~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { CLOCK_50 CLOCK_50~clkctrl } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.039 ns) + CELL(0.537 ns) 2.693 ns iDATA\[5\] 3 REG LCFF_X16_Y1_N5 1 " "Info: 3: + IC(1.039 ns) + CELL(0.537 ns) = 2.693 ns; Loc. = LCFF_X16_Y1_N5; Fanout = 1; REG Node = 'iDATA\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.576 ns" { CLOCK_50~clkctrl iDATA[5] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.04 % ) " "Info: Total cell delay = 1.536 ns ( 57.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.157 ns ( 42.96 % ) " "Info: Total interconnect delay = 1.157 ns ( 42.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl iDATA[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl iDATA[5] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.641 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns SW\[5\] 1 PIN PIN_AD13 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_AD13; Fanout = 2; PIN Node = 'SW\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { SW[5] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.419 ns) + CELL(0.149 ns) 2.557 ns iDATA\[5\]~feeder 2 COMB LCCOMB_X16_Y1_N4 1 " "Info: 2: + IC(1.419 ns) + CELL(0.149 ns) = 2.557 ns; Loc. = LCCOMB_X16_Y1_N4; Fanout = 1; COMB Node = 'iDATA\[5\]~feeder'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.568 ns" { SW[5] iDATA[5]~feeder } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.641 ns iDATA\[5\] 3 REG LCFF_X16_Y1_N5 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 2.641 ns; Loc. = LCFF_X16_Y1_N5; Fanout = 1; REG Node = 'iDATA\[5\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { iDATA[5]~feeder iDATA[5] } "NODE_NAME" } } { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 100 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.222 ns ( 46.27 % ) " "Info: Total cell delay = 1.222 ns ( 46.27 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.419 ns ( 53.73 % ) " "Info: Total interconnect delay = 1.419 ns ( 53.73 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.641 ns" { SW[5] iDATA[5]~feeder iDATA[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.641 ns" { SW[5] SW[5]~combout iDATA[5]~feeder iDATA[5] } { 0.000ns 0.000ns 1.419ns 0.000ns } { 0.000ns 0.989ns 0.149ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.693 ns" { CLOCK_50 CLOCK_50~clkctrl iDATA[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.693 ns" { CLOCK_50 CLOCK_50~combout CLOCK_50~clkctrl iDATA[5] } { 0.000ns 0.000ns 0.118ns 1.039ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.641 ns" { SW[5] iDATA[5]~feeder iDATA[5] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.641 ns" { SW[5] SW[5]~combout iDATA[5]~feeder iDATA[5] } { 0.000ns 0.000ns 1.419ns 0.000ns } { 0.000ns 0.989ns 0.149ns 0.084ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Dec 13 11:30:45 2007 " "Info: Processing ended: Thu Dec 13 11:30:45 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}