{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Dec 13 11:29:49 2007 " "Info: Processing started: Thu Dec 13 11:29:49 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SRAMtest -c SRAMtest " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SRAMtest -c SRAMtest" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_4 " "Info: Found entity 1: SEG7_LUT_4" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" {  } { { "SEG7_LUT.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAM_16Bit_512K.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAM_16Bit_512K.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAM_16Bit_512K " "Info: Found entity 1: SRAM_16Bit_512K" {  } { { "SRAM_16Bit_512K.v" "" { Text "G:/verilog/SRAMtest/SRAM_16Bit_512K.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Reset_Delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" {  } { { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAMtest.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAMtest.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAMtest " "Info: Found entity 1: SRAMtest" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SRAMtest " "Info: Elaborating entity \"SRAMtest\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 SRAMtest.v(82) " "Warning (10230): Verilog HDL assignment warning at SRAMtest.v(82): truncated value with size 32 to match size of target (2)" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[7\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[7\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[6\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[6\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[5\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[5\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[4\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[4\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[3\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[3\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[2\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[2\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[1\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[1\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Warning" "WVRFX_L2_VRFC_DRIVERLESS_OUTPUT_PORT" "LEDR\[0\] SRAMtest.v(22) " "Warning (10034): Output port \"LEDR\[0\]\" at SRAMtest.v(22) has no driver" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 22 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:r0 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:r0\"" {  } { { "SRAMtest.v" "r0" { Text "G:/verilog/SRAMtest/SRAMtest.v" 103 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 Reset_Delay.v(11) " "Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(11): truncated value with size 32 to match size of target (20)" {  } { { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SRAM_16Bit_512K SRAM_16Bit_512K:the_SRAM_16Bit_512K " "Info: Elaborating entity \"SRAM_16Bit_512K\" for hierarchy \"SRAM_16Bit_512K:the_SRAM_16Bit_512K\"" {  } { { "SRAMtest.v" "the_SRAM_16Bit_512K" { Text "G:/verilog/SRAMtest/SRAMtest.v" 122 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_4 SEG7_LUT_4:seg_4 " "Info: Elaborating entity \"SEG7_LUT_4\" for hierarchy \"SEG7_LUT_4:seg_4\"" {  } { { "SRAMtest.v" "seg_4" { Text "G:/verilog/SRAMtest/SRAMtest.v" 125 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}