?? sramtest.fnsim.qmsg
字號:
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Dec 11 20:58:38 2007 " "Info: Processing started: Tue Dec 11 20:58:38 2007" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off SRAMtest -c SRAMtest --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off SRAMtest -c SRAMtest --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT_4.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT_4.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT_4 " "Info: Found entity 1: SEG7_LUT_4" { } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SEG7_LUT.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SEG7_LUT.v" { { "Info" "ISGN_ENTITY_NAME" "1 SEG7_LUT " "Info: Found entity 1: SEG7_LUT" { } { { "SEG7_LUT.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAM_16Bit_512K.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAM_16Bit_512K.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAM_16Bit_512K " "Info: Found entity 1: SRAM_16Bit_512K" { } { { "SRAM_16Bit_512K.v" "" { Text "G:/verilog/SRAMtest/SRAM_16Bit_512K.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Reset_Delay.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file Reset_Delay.v" { { "Info" "ISGN_ENTITY_NAME" "1 Reset_Delay " "Info: Found entity 1: Reset_Delay" { } { { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "SRAMtest.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file SRAMtest.v" { { "Info" "ISGN_ENTITY_NAME" "1 SRAMtest " "Info: Found entity 1: SRAMtest" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 1 -1 0 } } } 0 0 "Found entity %1!d!: %2!s!" 0 0} } { } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "SRAMtest " "Info: Elaborating entity \"SRAMtest\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "16 1 SRAMtest.v(53) " "Warning (10230): Verilog HDL assignment warning at SRAMtest.v(53): truncated value with size 16 to match size of target (1)" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 53 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "iDATA SRAMtest.v(54) " "Warning (10240): Verilog HDL Always Construct warning at SRAMtest.v(54): inferring latch(es) for variable \"iDATA\", which holds its previous value in one or more paths through the always construct" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 54 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[15\] SRAMtest.v(34) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(34): inferred latch for \"iDATA\[15\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 34 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[14\] SRAMtest.v(34) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(34): inferred latch for \"iDATA\[14\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 34 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[13\] SRAMtest.v(34) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(34): inferred latch for \"iDATA\[13\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 34 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[12\] SRAMtest.v(34) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(34): inferred latch for \"iDATA\[12\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 34 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[11\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[11\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[10\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[10\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[9\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[9\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[8\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[8\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[7\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[7\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[6\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[6\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[5\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[5\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[4\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[4\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[3\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[3\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[2\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[2\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[1\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[1\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iDATA\[0\] SRAMtest.v(56) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(56): inferred latch for \"iDATA\[0\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 56 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "iADDR SRAMtest.v(54) " "Warning (10240): Verilog HDL Always Construct warning at SRAMtest.v(54): inferring latch(es) for variable \"iADDR\", which holds its previous value in one or more paths through the always construct" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 54 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[17\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[17\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[16\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[16\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[15\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[15\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[14\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[14\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[13\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[13\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[12\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[12\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[11\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[11\]\"" { } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } } } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
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