{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[10\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[10\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[9\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[9\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[8\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[8\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[7\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[7\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[6\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[6\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[5\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[5\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[4\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[4\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[3\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[3\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[2\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[2\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[1\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[1\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_L2_VRFC_LATCH_INFERRED" "iADDR\[0\] SRAMtest.v(36) " "Info (10041): Verilog HDL or VHDL info at SRAMtest.v(36): inferred latch for \"iADDR\[0\]\"" {  } { { "SRAMtest.v" "" { Text "G:/verilog/SRAMtest/SRAMtest.v" 36 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Reset_Delay Reset_Delay:r0 " "Info: Elaborating entity \"Reset_Delay\" for hierarchy \"Reset_Delay:r0\"" {  } { { "SRAMtest.v" "r0" { Text "G:/verilog/SRAMtest/SRAMtest.v" 62 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 20 Reset_Delay.v(11) " "Warning (10230): Verilog HDL assignment warning at Reset_Delay.v(11): truncated value with size 32 to match size of target (20)" {  } { { "Reset_Delay.v" "" { Text "G:/verilog/SRAMtest/Reset_Delay.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SRAM_16Bit_512K SRAM_16Bit_512K:the_SRAM_16Bit_512K " "Info: Elaborating entity \"SRAM_16Bit_512K\" for hierarchy \"SRAM_16Bit_512K:the_SRAM_16Bit_512K\"" {  } { { "SRAMtest.v" "the_SRAM_16Bit_512K" { Text "G:/verilog/SRAMtest/SRAMtest.v" 81 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT_4 SEG7_LUT_4:seg_4 " "Info: Elaborating entity \"SEG7_LUT_4\" for hierarchy \"SEG7_LUT_4:seg_4\"" {  } { { "SRAMtest.v" "seg_4" { Text "G:/verilog/SRAMtest/SRAMtest.v" 84 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "SEG7_LUT SEG7_LUT_4:seg_4\|SEG7_LUT:u0 " "Info: Elaborating entity \"SEG7_LUT\" for hierarchy \"SEG7_LUT_4:seg_4\|SEG7_LUT:u0\"" {  } { { "SEG7_LUT_4.v" "u0" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 17 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_WIDE" "iDIG seg_4 1 16 " "Warning: Port \"iDIG\" on the entity instantiation of \"seg_4\" is connected to a signal of width 1. The formal width of the signal in the module is 16.  Extra bits will be driven by GND." {  } { { "SRAMtest.v" "seg_4" { Text "G:/verilog/SRAMtest/SRAMtest.v" 84 0 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[14\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[14\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[13\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[13\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[12\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[12\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[11\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[11\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[10\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[10\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[9\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[9\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[8\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[8\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[7\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[7\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[6\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[6\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[5\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[5\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[4\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[4\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[3\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[3\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[2\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[2\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[1\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[1\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "SEG7_LUT_4:seg_4\|temp_DIG\[15\] data_in GND " "Warning: Reduced register \"SEG7_LUT_4:seg_4\|temp_DIG\[15\]\" with stuck data_in port to stuck value GND" {  } { { "SEG7_LUT_4.v" "" { Text "G:/verilog/SRAMtest/SEG7_LUT_4.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 20 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 20 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Dec 11 20:58:40 2007 " "Info: Processing ended: Tue Dec 11 20:58:40 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}