module bldcm_con_tb  ;    wire  [5:0]  pwmout   ;   reg  [2:0]  hall   ;   reg[2:0] current_state,next_state;  reg    clk1,clk2   ;   reg    dir   ;   parameter CLK_PERIOD = 2;  parameter S0 = 3'b000,            S1 = 3'b100,            S2 = 3'b110,            S3 = 3'b111,            S4 = 3'b011,            S5 = 3'b001;      initial  begin  clk1 = 1'b0;  clk2 = 1'b0;  dir = 1'b0;  forever     #(CLK_PERIOD/2) clk1 = ~clk1;    end      initial   begin    clk2 = 1'b0;    forever     #(CLK_PERIOD*10) clk2 = ~clk2;      end      always @(posedge clk2)  begin   #(CLK_PERIOD/2)current_state <= next_state;   hall = current_state;  end always @(posedge clk2)begin    case(current_state)    S0:       next_state = S1;    S1:       next_state = S2;    S2:       next_state = S3;    S3:         next_state = S4;    S4:         next_state = S5;    S5:         next_state = S0;    default:        next_state = S0;    endcase  end     bldcm_con     DUT  (        .pwmout (pwmout ) ,      .hall (hall ) ,      .clk (clk1 ) ,      .dir (dir ) ); endmodule