// VERILOG TestFixture Template produced by ngd2ver M1.4.12// Design file: time_sim.nga// Date:Tue Jan  6 18:48:58 1998// ATTENTION: This file was created by NGD2VER and may therefore be overwritten// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to// a new name, or 'paste' this text into another file, to avoid accidental loss// of data.`timescale 1 ns/1 psmodule test;  reg IN1;  reg IN2;  reg DATA;  reg CLK;  reg LOAD;  wire OUT1;  reg GSR;  `define GSR_SIGNAL test.GSR  reg GTS;  `define GTS_SIGNAL test.GTS  gate_clock2 uut ( .IN1 (IN1) , .IN2 (IN2) , .DATA (DATA) , .CLK (CLK) , .LOAD (LOAD) , .OUT1 (OUT1) );  initial begin    $timeformat(-9,3,"ns",12);    $shm_open("time_sim.shm");    $shm_probe("AS");  end  initial begin    $display("           T IIDCLO");    $display("           i NNALOU");    $display("           m 12TKAT");    $display("           e   A D1");    $monitor("%t",$realtime,, IN1, IN2, DATA, CLK, LOAD, OUT1 );  end  initial begin      `GSR_SIGNAL = 1;      `GTS_SIGNAL = 0;    #100      `GSR_SIGNAL = 0;      IN1 = 0 ;      IN2 = 0 ;      DATA = 0 ;      CLK = 0 ;      LOAD = 0 ;    #1000 $stop;    // #1000 $finish;  endendmodule