// Xilinx Verilog produced by program ngd2ver, Version M1.4.12// Date: Tue Jan  6 18:48:58 1998// Design file: time_sim.nga// Device: 4005epc84-2`timescale 1 ns/1 ps`uselib dir=/home/zeppelin2/tech_apps/m1_4.12/verilog/data libext=.vmd  module gate_clock2 (IN1, IN2, DATA, CLK, LOAD, OUT1);    input IN1;    input IN2;    input DATA;    input CLK;    input LOAD;    output OUT1;    wire n57, n58, n59, n60, n61, n85, n_1, n83, n84, OUT1_reg_GSR_OR,     \U40/$1I20_GTS_TRI , \U38/clkio_bufsig , \U41/2_0 ,     \U40/$1I20_GTS_TRI_2_INV , GND;    `ifdef GSR_SIGNAL      wire GSR = `GSR_SIGNAL ;    `else      wire GSR ;    `endif    `ifdef GTS_SIGNAL      wire GTS = `GTS_SIGNAL ;    `else      wire GTS ;    `endif    initial $sdf_annotate("time_sim.sdf");    X_BUF U35 (.IN (IN1), .OUT (n57));    X_BUF U36 (.IN (IN2), .OUT (n58));    X_BUF U37 (.IN (DATA), .OUT (n59));    X_BUF U39 (.IN (LOAD), .OUT (n61));    X_FF OUT1_reg (.IN (n59), .CLK (n84), .CE (n61), .SET (GND), .RST     (OUT1_reg_GSR_OR), .OUT (n85));    X_INV U43 (.IN (n_1), .OUT (n84));    X_IPAD IN1_PAD (.PAD (IN1));    X_IPAD IN2_PAD (.PAD (IN2));    X_IPAD DATA_PAD (.PAD (DATA));    X_IPAD CLK_PAD (.PAD (CLK));    X_IPAD LOAD_PAD (.PAD (LOAD));    X_OPAD OUT1_PAD (.PAD (OUT1));    X_ZERO n83_ZERO (.OUT (n83));    X_OR2 OUT1_reg_GSR_OR_23 (.IN0 (n83), .IN1 (GSR), .OUT (OUT1_reg_GSR_OR));    X_BUF \U40/$1I20  (.IN (n85), .OUT (\U40/$1I20_GTS_TRI ));    X_TRI \U40/$1I20_GTS_TRI_24  (.IN (\U40/$1I20_GTS_TRI ), .OUT (OUT1), .CTL     (\U40/$1I20_GTS_TRI_2_INV ));    X_CKBUF \U38/clkbuf  (.IN (\U38/clkio_bufsig ), .OUT (n60));    X_BUF \U38/clkio_buf  (.IN (CLK), .OUT (\U38/clkio_bufsig ));    X_AND2 \U41/n_1/2_0  (.IN0 (n57), .IN1 (n58), .OUT (\U41/2_0 ));    X_AND2 \U41/n_1  (.IN0 (\U41/2_0 ), .IN1 (n60), .OUT (n_1));    X_INV \U40/$1I20_GTS_TRI_2_INV_25  (.IN (GTS), .OUT     (\U40/$1I20_GTS_TRI_2_INV ));    X_ZERO GND_26 (.OUT (GND));    X_PD NGD2VER_PD_21 (.OUT (GSR) );    X_PD NGD2VER_PD_22 (.OUT (GTS) );  endmodule