--------------------------------------------------------------------------------Xilinx TRACE, Version M1.4.12Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design file:              gate_clock2.ncdPhysical constraint file: gate_clock2.pcfDevice,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)Report level:             summary report--------------------------------------------------------------------------------WARNING:bastw:172 - No timing constraints found, doing advanced analysis with   offsets.================================================================================Timing constraint: Default period analysis for net n_1 2 items analyzed, 0 timing errors detected. Minimum period is   6.088ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET IN BEFORE analysis for clock "n_1" 2 items analyzed, 0 timing errors detected. Minimum allowable offset is   0.492ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET OUT AFTER analysis for clock "n_1" 1 item analyzed, 0 timing errors detected. Maximum allowable offset is  18.222ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default path analysis 4 items analyzed, 0 timing errors detected. Maximum delay is  11.784ns.--------------------------------------------------------------------------------All constraints were met.Timing summary:---------------Timing errors: 0  Score: 0Constraints cover 10 paths, 0 nets, and 8 connections (100.0% coverage)Design statistics:   Minimum period:   6.088ns (Maximum frequency: 164.258MHz)   Maximum combinational path delay:  11.784ns   Minimum input arrival time before clock:   0.492ns   Maximum output required time before clock:  18.222nsAnalysis completed Tue Jan  6 18:48:50 1998--------------------------------------------------------------------------------