Xilinx Mapping Report File for Design "gate_clock"          Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design Information------------------Command Line   : map gate_clock.ngd -o map.ncd gate_clock.pcf Target Device  : x4005eTarget Package : pc84Target Speed   : -2Mapper Version : xc4000e -- M1.4.12Mapped Date    : Tue Jan  6 16:47:48 1998Design Summary--------------   Number of errors:        0   Number of warnings:      2   Number of CLBs:              1 out of   196    1%      CLB Flip Flops:       1      4 input LUTs:         1      3 input LUTs:         0   Number of bonded IOBs:       6 out of    61    9%      IOB Flops:            0      IOB Latches:          0   Number of global buffers:    3 out of     8   37%   Number of secondary CLKs:    3 out of     4   75%Total equivalent gate count for design: 12Additional JTAG gate count for IOBs:    288Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - Design AttributesSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - Added LogicSection 7 - Expanded LogicSection 8 - Signal Cross-ReferenceSection 9 - Symbol Cross-ReferenceSection 10 - IOB PropertiesSection 11 - RPMsSection 12 - Guide ReportSection 1 - Errors------------------Section 2 - Warnings--------------------WARNING:baste:21 - Chipcheck: The signal "n49" is connected to the asynchronous   set/reset of every flip-flop in the design.  Using the dedicated GSR/GR   (global set/reset) pin on the STARTUP component will reduce the ammount of   routing resources required to implement the design.  To use GSR/GR,   disconnect the "n49" signal from the reset pin of every flip-flop in the   design, and connect it to the GSR/GR pin of the STARTUP component.  Note that   all flip-flops on the device will be cleared when GSR/GR goes active.WARNING:baste:24 - All of the external outputs in this design are using   slew-rate-limited output drivers.  The delay on speed critical outputs can be   dramatically reduced by designating them as fast outputs in the original   design.  Please see your vendor interface documentation for specific   information on how to do this within your design-entry tool.   Note: You should be careful not to designate too many outputs which switch   together as fast, because this can cause excessive ground bounce.  For more   information on this subject, please refer to the IOB switching characteristic   guidelines for the device you are using in the Programmable Logic Data Book.Section 3 - Design Attributes-----------------------------Section 4 - Removed Logic Summary---------------------------------   1 block(s) removed   1 block(s) optimized away   1 signal(s) mergedSection 5 - Removed Logic-------------------------Block "U39" (INV) redundant - removed.Block "n49.ZERO" (X_ZERO) removed due to optimization.Merged Signal(s):The signal "n50" was merged into signal "n_1".Section 6 - Added Logic-----------------------Section 7 - Expanded Logic--------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 8 - Signal Cross-Reference----------------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 9 - Symbol Cross-Reference----------------------------------To enable this section, set the environment variable MAP_REPORT_DETAIL to TRUEand rerun MAP.Section 10 - IOB Properties---------------------------"OUT1" (IOB) : SLEW=SLOWSection 11 - RPMs-----------------Section 12 - Guide Report-------------------------Guide not run on this design.