-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12-- Date: Tue Jan  6 16:45:49 1998-- Design file: time_sim.nga-- Device: 4005epc84-2----- CELL ROC ------- Model for  Reset-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity ROC is    generic ( InstancePath: STRING := "*";              WIDTH : Time := 0 ns) ;    port( O : out std_ulogic := '1' ) ;    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;end ROC ;architecture ROC_V of ROC isattribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;begin    ONE_SHOT: process    begin      if (WIDTH <= 0 ns) then         assert FALSE report         "*** Error: a positive value of WIDTH must be specified ***"         severity failure;      else         wait for WIDTH;         O <= '0' ;      end if;      wait;    end process ONE_SHOT ;end ROC_V ;configuration CFG_ROC_V of ROC is    for ROC_V    end for ;end CFG_ROC_V ;----- CELL TOC ------- Model for  Tristate-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity TOC is    generic ( InstancePath: STRING := "*");    port( O : out std_ulogic := '0' ) ;    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;end TOC ;architecture TOC_V of TOC isattribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;begin    ONE_SHOT: process    begin      wait;    end process ONE_SHOT ;end TOC_V ;configuration CFG_TOC_V of TOC is    for TOC_V    end for ;end CFG_TOC_V ;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity GATE_CLOCK2 is  port (    IN1 : in STD_LOGIC := 'X' ;    IN2 : in STD_LOGIC := 'X' ;    DATA : in STD_LOGIC := 'X' ;    CLK : in STD_LOGIC := 'X' ;    LOAD : in STD_LOGIC := 'X' ;    OUT1 : out STD_LOGIC   ) ;end GATE_CLOCK2 ;architecture STRUCTURE of GATE_CLOCK2 is  component ROC       port ( O : out STD_ULOGIC ) ;  end component ;  component TOC       port ( O : out STD_ULOGIC ) ;  end component ;  signal N27 , N28 , N29 , N30 , N31 , N55 , N_1 , N53 , N54 , OUT1_REG_GSR_OR   , U40_1I20_GTS_TRI , U38_CLKIO_BUFSIG , U41_2_0 , U40_1I20_GTS_TRI_2_INV ,   GND , GSR , GTS : STD_LOGIC ;  begin    U35 : X_BUF       port map ( I => IN1 , O => N27 ) ;    U36 : X_BUF       port map ( I => IN2 , O => N28 ) ;    U37 : X_BUF       port map ( I => DATA , O => N29 ) ;    U39 : X_BUF       port map ( I => LOAD , O => N31 ) ;    OUT1_REG : X_FF       port map ( I => N29 , CLK => N54 , CE => N31 , SET => GND ,       RST => OUT1_REG_GSR_OR , O => N55 ) ;    U43 : X_INV       port map ( I => N_1 , O => N54 ) ;    N53_ZERO : X_ZERO       port map ( O => N53 ) ;    OUT1_REG_GSR_OR_0 : X_OR2       port map ( I0 => N53 , I1 => GSR , O => OUT1_REG_GSR_OR ) ;    U40_1I20 : X_BUF       port map ( I => N55 , O => U40_1I20_GTS_TRI ) ;    U40_1I20_GTS_TRI_1 : X_TRI       port map ( I => U40_1I20_GTS_TRI , O => OUT1 ,       CTL => U40_1I20_GTS_TRI_2_INV ) ;    U38_CLKBUF : X_CKBUF       port map ( I => U38_CLKIO_BUFSIG , O => N30 ) ;    U38_CLKIO_BUF : X_BUF       port map ( I => CLK , O => U38_CLKIO_BUFSIG ) ;    U41_N_1_2_0 : X_AND2       port map ( I0 => N27 , I1 => N28 , O => U41_2_0 ) ;    U41_N_1 : X_AND2       port map ( I0 => U41_2_0 , I1 => N30 , O => N_1 ) ;    U40_1I20_GTS_TRI_2_INV_2 : X_INV       port map ( I => GTS , O => U40_1I20_GTS_TRI_2_INV ) ;    GND_3 : X_ZERO       port map ( O => GND ) ;    ROC_NGD2VHDL : ROC       port map ( O => GSR ) ;    TOC_NGD2VHDL : TOC       port map ( O => GTS ) ;end STRUCTURE ;