// VERILOG TestFixture Template produced by ngd2ver M1.4.12// Design file: time_sim.nga// Date:Tue Jan  6 19:20:57 1998// ATTENTION: This file was created by NGD2VER and may therefore be overwritten// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to// a new name, or 'paste' this text into another file, to avoid accidental loss// of data.`timescale 1 ns/1 psmodule test;  reg A;  reg B;  wire OP_OUT;  reg [1:0] OPCODE;  reg GTS;  `define GTS_SIGNAL test.GTS  parameter1 uut ( .A (A) , .B (B) , .OP_OUT (OP_OUT) , .OPCODE (OPCODE) );  initial begin    $timeformat(-9,3,"ns",12);    $shm_open("time_sim.shm");    $shm_probe("AS");  end  initial begin    $display("           T ABOO");    $display("           i   PP");    $display("           m   _C");    $display("           e   OO");    $display("               UD");    $display("               TE");    $display("                [");    $display("                1");    $display("                :");    $display("                0");    $display("                ]");    $monitor("%t",$realtime,, A, B, OP_OUT, "%h", OPCODE );  end  initial begin      `GTS_SIGNAL = 0;    #100      A = 0 ;      B = 0 ;      OPCODE = 0 ;    #1000 $stop;    // #1000 $finish;  endendmodule