?? time_sim.tv
字號:
// VERILOG TestFixture Template produced by ngd2ver M1.4.12// Design file: time_sim.nga// Date:Tue Jan 6 18:46:27 1998// ATTENTION: This file was created by NGD2VER and may therefore be overwritten// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to// a new name, or 'paste' this text into another file, to avoid accidental loss// of data.`timescale 1 ns/1 psmodule test; reg A_CHECK; reg B_CHECK; reg RESET; reg CLOCK; reg CLKEN; reg A_TICK; reg B_TICK; wire ST_A; wire ST_B; reg GSR; `define GSR_SIGNAL test.GSR reg GTS; `define GTS_SIGNAL test.GTS gate_reduce uut ( .A_CHECK (A_CHECK) , .B_CHECK (B_CHECK) , .RESET (RESET) , .CLOCK (CLOCK) , .CLKEN (CLKEN) , .A_TICK (A_TICK) , .B_TICK (B_TICK) , .ST_A (ST_A) , .ST_B (ST_B) ); initial begin $timeformat(-9,3,"ns",12); $shm_open("time_sim.shm"); $shm_probe("AS"); end initial begin $display(" T ABRCCABSS"); $display(" i __ELL__TT"); $display(" m CCSOKTT__"); $display(" e HHECEIIAB"); $display(" EETKNCC "); $display(" CC KK "); $display(" KK "); $monitor("%t",$realtime,, A_CHECK, B_CHECK, RESET, CLOCK, CLKEN, A_TICK, B_TICK, ST_A, ST_B ); end initial begin `GSR_SIGNAL = 1; `GTS_SIGNAL = 0; #100 `GSR_SIGNAL = 0; A_CHECK = 0 ; B_CHECK = 0 ; RESET = 0 ; CLOCK = 0 ; CLKEN = 0 ; A_TICK = 0 ; B_TICK = 0 ; #1000 $stop; // #1000 $finish; endendmodule
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