--------------------------------------------------------------------------------Xilinx TRACE, Version M1.4.12Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design file:              gate_reduce.ncdPhysical constraint file: gate_reduce.pcfDevice,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)Report level:             summary report--------------------------------------------------------------------------------WARNING:bastw:172 - No timing constraints found, doing advanced analysis with   offsets.================================================================================Timing constraint: Default period analysis for net n62 1865 items analyzed, 0 timing errors detected. Minimum period is  31.457ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET IN BEFORE analysis for clock "n62" 374 items analyzed, 0 timing errors detected. Minimum allowable offset is  27.531ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET OUT AFTER analysis for clock "n62" 2 items analyzed, 0 timing errors detected. Maximum allowable offset is  17.841ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default path analysis 46 items analyzed, 0 timing errors detected. Maximum delay is  13.902ns.--------------------------------------------------------------------------------All constraints were met.Timing summary:---------------Timing errors: 0  Score: 0Constraints cover 2215 paths, 0 nets, and 463 connections (100.0% coverage)Design statistics:   Minimum period:  31.457ns (Maximum frequency:  31.789MHz)   Maximum combinational path delay:  13.902ns   Minimum input arrival time before clock:  27.531ns   Maximum output required time before clock:  17.841nsAnalysis completed Tue Jan  6 18:46:15 1998--------------------------------------------------------------------------------