?? time_sim.sdf
字號:
(PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U259) (DELAY (ABSOLUTE (PORT IN (1208:1208:1208) (1208:1208:1208)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_XOR2") (INSTANCE U261) (DELAY (ABSOLUTE (PORT IN0 (1335:1335:1335) (1335:1335:1335)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1317:1317:1317) (1317:1317:1317)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U262) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (1613:1613:1613) (1613:1613:1613)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<1\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1212:1212:1212) (1212:1212:1212)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4609:4609:4609) (4609:4609:4609)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_XOR2") (INSTANCE U263) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1376:1376:1376) (1376:1376:1376)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U264) (DELAY (ABSOLUTE (PORT IN0 (1513:1513:1513) (1513:1513:1513)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1576:1576:1576) (1576:1576:1576)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U265) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (1753:1753:1753) (1753:1753:1753)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U266) (DELAY (ABSOLUTE (PORT IN0 (2610:2610:2610) (2610:2610:2610)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1886:1886:1886) (1886:1886:1886)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<2\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1212:1212:1212) (1212:1212:1212)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4571:4571:4571) (4571:4571:4571)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U268) (DELAY (ABSOLUTE (PORT IN0 (1362:1362:1362) (1362:1362:1362)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2087:2087:2087) (2087:2087:2087)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U269) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1010:1010:1010) (1010:1010:1010)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U270) (DELAY (ABSOLUTE (PORT IN0 (2424:2424:2424) (2424:2424:2424)) (IOPATH IN0 OUT (1600:1600:1600) (1600:1600:1600)) (PORT IN1 (0:0:0) (0:0:0)) (IOPATH IN1 OUT (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_XOR2") (INSTANCE U271) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1241:1241:1241) (1241:1241:1241)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U272) (DELAY (ABSOLUTE (PORT IN0 (1625:1625:1625) (1625:1625:1625)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1210:1210:1210) (1210:1210:1210)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U273) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (1600:1600:1600) (1600:1600:1600)) (PORT IN1 (1258:1258:1258) (1258:1258:1258)) (IOPATH IN1 OUT (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ECNT_reg\<4\>) (DELAY (ABSOLUTE (PORT IN (820:820:820) (820:820:820)) (PORT CLK (1212:1212:1212) (1212:1212:1212)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3938:3938:3938) (3938:3938:3938)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_XOR2") (INSTANCE U274) (DELAY (ABSOLUTE (PORT IN0 (1324:1324:1324) (1324:1324:1324)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1179:1179:1179) (1179:1179:1179)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U275) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1370:1370:1370) (1370:1370:1370)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U276) (DELAY (ABSOLUTE (PORT IN0 (1464:1464:1464) (1464:1464:1464)) (IOPATH IN0 OUT (1600:1600:1600) (1600:1600:1600)) (PORT IN1 (0:0:0) (0:0:0)) (IOPATH IN1 OUT (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_XOR2") (INSTANCE U277) (DELAY (ABSOLUTE (PORT IN0 (1405:1405:1405) (1405:1405:1405)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1782:1782:1782) (1782:1782:1782)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U278) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (1600:1600:1600) (1600:1600:1600)) (PORT IN1 (1258:1258:1258) (1258:1258:1258)) (IOPATH IN1 OUT (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ECNT_reg\<1\>) (DELAY (ABSOLUTE (PORT IN (820:820:820) (820:820:820)) (PORT CLK (1212:1212:1212) (1212:1212:1212)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3938:3938:3938) (3938:3938:3938)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U279) (DELAY (ABSOLUTE (PORT IN (1313:1313:1313) (1313:1313:1313)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U281) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U282) (DELAY (ABSOLUTE (PORT IN (1319:1319:1319) (1319:1319:1319)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U283) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1225:1225:1225) (1225:1225:1225)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U284) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (4781:4781:4781) (4781:4781:4781)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U285) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (4266:4266:4266) (4266:4266:4266)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/CLREVENT_reg) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1206:1206:1206) (1206:1206:1206)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3667:3667:3667) (3667:3667:3667)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U286) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U287) (DELAY (ABSOLUTE (PORT IN (1900:1900:1900) (1900:1900:1900)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U288) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2556:2556:2556) (2556:2556:2556)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U289) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2424:2424:2424) (2424:2424:2424)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U290) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (6146:6146:6146) (6146:6146:6146)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U291) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U292) (DELAY (ABSOLUTE (PORT IN (1903:1903:1903) (1903:1903:1903)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U293) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1198:1198:1198) (1198:1198:1198)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U294) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0))?? 快捷鍵說明
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