--------------------------------------------------------------------------------Xilinx TRACE, Version M1.4.12Copyright (c) 1995-1997 Xilinx, Inc.  All rights reserved.Design file:              gate_reduce.ncdPhysical constraint file: gate_reduce.pcfDevice,speed:             xc4005e,-2 (x1_0.86  PRELIMINARY)Report level:             summary report--------------------------------------------------------------------------------WARNING:bastw:172 - No timing constraints found, doing advanced analysis with   offsets.================================================================================Timing constraint: Default period analysis for net n62 2428 items analyzed, 0 timing errors detected. Minimum period is  38.134ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET IN BEFORE analysis for clock "n62" 450 items analyzed, 0 timing errors detected. Minimum allowable offset is  32.919ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default OFFSET OUT AFTER analysis for clock "n62" 2 items analyzed, 0 timing errors detected. Maximum allowable offset is  16.765ns.--------------------------------------------------------------------------------================================================================================Timing constraint: Default path analysis 46 items analyzed, 0 timing errors detected. Maximum delay is  12.833ns.--------------------------------------------------------------------------------All constraints were met.Timing summary:---------------Timing errors: 0  Score: 0Constraints cover 2824 paths, 0 nets, and 520 connections (100.0% coverage)Design statistics:   Minimum period:  38.134ns (Maximum frequency:  26.223MHz)   Maximum combinational path delay:  12.833ns   Minimum input arrival time before clock:  32.919ns   Maximum output required time before clock:  16.765nsAnalysis completed Tue Jan  6 18:42:10 1998--------------------------------------------------------------------------------