?? time_sim.sdf
字號:
(PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4503:4503:4503) (4503:4503:4503)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U292) (DELAY (ABSOLUTE (PORT IN0 (3451:3451:3451) (3451:3451:3451)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2475:2475:2475) (2475:2475:2475)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U293) (DELAY (ABSOLUTE (PORT IN (1638:1638:1638) (1638:1638:1638)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U295) (DELAY (ABSOLUTE (PORT IN0 (3169:3169:3169) (3169:3169:3169)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2400:2400:2400) (2400:2400:2400)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U296) (DELAY (ABSOLUTE (PORT IN (1416:1416:1416) (1416:1416:1416)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<2\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1206:1206:1206) (1206:1206:1206)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3883:3883:3883) (3883:3883:3883)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<1\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4503:4503:4503) (4503:4503:4503)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U298) (DELAY (ABSOLUTE (PORT IN0 (3169:3169:3169) (3169:3169:3169)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2400:2400:2400) (2400:2400:2400)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U299) (DELAY (ABSOLUTE (PORT IN (1416:1416:1416) (1416:1416:1416)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U301) (DELAY (ABSOLUTE (PORT IN0 (1594:1594:1594) (1594:1594:1594)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1556:1556:1556) (1556:1556:1556)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U302) (DELAY (ABSOLUTE (PORT IN (2094:2094:2094) (2094:2094:2094)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<4\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1194:1194:1194) (1194:1194:1194)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4611:4611:4611) (4611:4611:4611)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<3\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1206:1206:1206) (1206:1206:1206)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3883:3883:3883) (3883:3883:3883)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U304) (DELAY (ABSOLUTE (PORT IN0 (1594:1594:1594) (1594:1594:1594)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1828:1828:1828) (1828:1828:1828)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U305) (DELAY (ABSOLUTE (PORT IN (2094:2094:2094) (2094:2094:2094)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U307) (DELAY (ABSOLUTE (PORT IN0 (2762:2762:2762) (2762:2762:2762)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2400:2400:2400) (2400:2400:2400)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U308) (DELAY (ABSOLUTE (PORT IN (1639:1639:1639) (1639:1639:1639)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<6\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1206:1206:1206) (1206:1206:1206)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4280:4280:4280) (4280:4280:4280)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/ZCNT_reg\<5\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1194:1194:1194) (1194:1194:1194)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4611:4611:4611) (4611:4611:4611)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U310) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U311) (DELAY (ABSOLUTE (PORT IN (1832:1832:1832) (1832:1832:1832)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U312) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1046:1046:1046) (1046:1046:1046)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U313) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2705:2705:2705) (2705:2705:2705)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U314) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (6453:6453:6453) (6453:6453:6453)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U315) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U316) (DELAY (ABSOLUTE (PORT IN (2050:2050:2050) (2050:2050:2050)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U317) (DELAY (ABSOLUTE (PORT IN0 (1037:1037:1037) (1037:1037:1037)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (0:0:0) (0:0:0)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U318) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1373:1373:1373) (1373:1373:1373)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U319) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (1600:1600:1600) (1600:1600:1600)) (PORT IN1 (6759:6759:6759) (6759:6759:6759)) (IOPATH IN1 OUT (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1\/CLREVENT_reg) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1212:1212:1212) (1212:1212:1212)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3598:3598:3598) (3598:3598:3598)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U320) (DELAY (ABSOLUTE (PORT IN0 (2205:2205:2205) (2205:2205:2205)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (1317:1317:1317) (1317:1317:1317)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U321) (DELAY (ABSOLUTE (PORT IN0 (2205:2205:2205) (2205:2205:2205)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (1035:1035:1035) (1035:1035:1035)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/DCNT_reg\<1\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1212:1212:1212) (1212:1212:1212)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4268:4268:4268) (4268:4268:4268)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/DCNT_reg\<0\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1212:1212:1212) (1212:1212:1212)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4268:4268:4268) (4268:4268:4268)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U322) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) )?? 快捷鍵說明
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