?? time_sim.sdf
字號:
) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U323) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1305:1305:1305) (1305:1305:1305)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U324) (DELAY (ABSOLUTE (PORT IN0 (3619:3619:3619) (3619:3619:3619)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (3089:3089:3089) (3089:3089:3089)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U325) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (5270:5270:5270) (5270:5270:5270)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U326) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U327) (DELAY (ABSOLUTE (PORT IN (2951:2951:2951) (2951:2951:2951)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U328) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1361:1361:1361) (1361:1361:1361)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U329) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2476:2476:2476) (2476:2476:2476)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U330) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (2420:2420:2420) (2420:2420:2420)) (PORT IN1 (5696:5696:5696) (5696:5696:5696)) (IOPATH IN1 OUT (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/CLREVENT_reg) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1200:1200:1200) (1200:1200:1200)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4087:4087:4087) (4087:4087:4087)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U331) (DELAY (ABSOLUTE (PORT IN0 (3601:3601:3601) (3601:3601:3601)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2360:2360:2360) (2360:2360:2360)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U332) (DELAY (ABSOLUTE (PORT IN (3542:3542:3542) (3542:3542:3542)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U334) (DELAY (ABSOLUTE (PORT IN0 (3601:3601:3601) (3601:3601:3601)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2360:2360:2360) (2360:2360:2360)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U335) (DELAY (ABSOLUTE (PORT IN (3542:3542:3542) (3542:3542:3542)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/ZCNT_reg\<1\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4413:4413:4413) (4413:4413:4413)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/ZCNT_reg\<0\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4413:4413:4413) (4413:4413:4413)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U337) (DELAY (ABSOLUTE (PORT IN0 (3601:3601:3601) (3601:3601:3601)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2703:2703:2703) (2703:2703:2703)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U338) (DELAY (ABSOLUTE (PORT IN (2092:2092:2092) (2092:2092:2092)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U340) (DELAY (ABSOLUTE (PORT IN0 (3601:3601:3601) (3601:3601:3601)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2703:2703:2703) (2703:2703:2703)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U341) (DELAY (ABSOLUTE (PORT IN (2092:2092:2092) (2092:2092:2092)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/ZCNT_reg\<3\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4413:4413:4413) (4413:4413:4413)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/ZCNT_reg\<2\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (4413:4413:4413) (4413:4413:4413)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U343) (DELAY (ABSOLUTE (PORT IN0 (3831:3831:3831) (3831:3831:3831)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2556:2556:2556) (2556:2556:2556)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U344) (DELAY (ABSOLUTE (PORT IN (2198:2198:2198) (2198:2198:2198)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U346) (DELAY (ABSOLUTE (PORT IN0 (3831:3831:3831) (3831:3831:3831)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2556:2556:2556) (2556:2556:2556)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U347) (DELAY (ABSOLUTE (PORT IN (2198:2198:2198) (2198:2198:2198)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/ZCNT_reg\<5\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3724:3724:3724) (3724:3724:3724)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/ZCNT_reg\<4\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3724:3724:3724) (3724:3724:3724)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U349) (DELAY (ABSOLUTE (PORT IN0 (2955:2955:2955) (2955:2955:2955)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (2287:2287:2287) (2287:2287:2287)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U350) (DELAY (ABSOLUTE (PORT IN (1593:1593:1593) (1593:1593:1593)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U352) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U353) (DELAY (ABSOLUTE (PORT IN (1457:1457:1457) (1457:1457:1457)) (IOPATH IN OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U354) (DELAY (ABSOLUTE (PORT IN0 (1169:1169:1169) (1169:1169:1169)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (0:0:0) (0:0:0)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U355) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (4303:4303:4303) (4303:4303:4303)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U356) (DELAY (ABSOLUTE (PORT IN0 (0:0:0) (0:0:0)) (IOPATH IN0 OUT (1600:1600:1600) (1600:1600:1600)) (PORT IN1 (5097:5097:5097) (5097:5097:5097)) (IOPATH IN1 OUT (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0\/ZCNT_reg\<6\>) (DELAY (ABSOLUTE (PORT IN (0:0:0) (0:0:0)) (PORT CLK (1225:1225:1225) (1225:1225:1225)) (IOPATH CLK OUT (2820:2820:2820) (0:0:0)) (PORT CE (3954:3954:3954) (3954:3954:3954)) (IOPATH SET OUT (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST OUT (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (SETUP RST (posedge CLK) (0:0:0)) (SETUP CE (posedge CLK) (0:0:0)) (SETUP IN (posedge CLK) (0:0:0)) (HOLD RST (posedge CLK) (0:0:0)) (HOLD CE (posedge CLK) (0:0:0)) (HOLD IN (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U357) (DELAY (ABSOLUTE (PORT IN0 (4148:4148:4148) (4148:4148:4148)) (IOPATH IN0 OUT (0:0:0) (0:0:0)) (PORT IN1 (1759:1759:1759) (1759:1759:1759)) (IOPATH IN1 OUT (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U359) (DELAY (ABSOLUT?? 快捷鍵說明
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