-- Xilinx VHDL produced by program ngd2vhdl, Version M1.4.12-- Date: Tue Jan  6 16:43:16 1998-- Design file: time_sim.nga-- Device: 4005epc84-2----- CELL ROC ------- Model for  Reset-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity ROC is    generic ( InstancePath: STRING := "*";              WIDTH : Time := 0 ns) ;    port( O : out std_ulogic := '1' ) ;    attribute VITAL_LEVEL0 of ROC : entity is TRUE ;end ROC ;architecture ROC_V of ROC isattribute VITAL_LEVEL0 of ROC_V : architecture is TRUE ;begin    ONE_SHOT: process    begin      if (WIDTH <= 0 ns) then         assert FALSE report         "*** Error: a positive value of WIDTH must be specified ***"         severity failure;      else         wait for WIDTH;         O <= '0' ;      end if;      wait;    end process ONE_SHOT ;end ROC_V ;configuration CFG_ROC_V of ROC is    for ROC_V    end for ;end CFG_ROC_V ;----- CELL TOC ------- Model for  Tristate-On-Configuration Celllibrary IEEE;use IEEE.std_logic_1164.all;use IEEE.VITAL_Timing.all;entity TOC is    generic ( InstancePath: STRING := "*");    port( O : out std_ulogic := '0' ) ;    attribute VITAL_LEVEL0 of TOC : entity is TRUE ;end TOC ;architecture TOC_V of TOC isattribute VITAL_LEVEL0 of TOC_V : architecture is TRUE ;begin    ONE_SHOT: process    begin      wait;    end process ONE_SHOT ;end TOC_V ;configuration CFG_TOC_V of TOC is    for TOC_V    end for ;end CFG_TOC_V ;library IEEE;use IEEE.STD_LOGIC_1164.ALL;library SIMPRIM;use SIMPRIM.VCOMPONENTS.ALL;use SIMPRIM.VPACKAGE.ALL;entity GATE_REDUCE is  port (    A_CHECK : in STD_LOGIC := 'X' ;    B_CHECK : in STD_LOGIC := 'X' ;    RESET : in STD_LOGIC := 'X' ;    CLOCK : in STD_LOGIC := 'X' ;    CLKEN : in STD_LOGIC := 'X' ;    A_TICK : in STD_LOGIC := 'X' ;    B_TICK : in STD_LOGIC := 'X' ;    ST_A : out STD_LOGIC ;    ST_B : out STD_LOGIC   ) ;end GATE_REDUCE ;architecture STRUCTURE of GATE_REDUCE is  component ROC       port ( O : out STD_ULOGIC ) ;  end component ;  component TOC       port ( O : out STD_ULOGIC ) ;  end component ;  signal N14 , N15 , N16 , N17 , N18 , N19 , N20 , N335 , N336 , I_0_N1163 ,   I_0_ST_INT446 , I_1_ST_INT446 , N154 , N153 , N152 , I_1_EQ2 , I_1_N283 ,   I_1_EQ2282 , N155 , N140 , I_1_N301 , I_0_CLRZERO , I_0_CLRZERO309 , I_0_N310   , N156 , N139 , N157 , N158 , N94 , N119 , I_0_EQ2 , I_0_EQ2282 , I_0_N283 ,   N161 , N160 , N159 , N162 , I_0_N301 , I_0_N292 , N122 , N118 , I_0_ECNT_E ,   I_0_ECNT_E434 , I_0_N256 , N163 , N164 , N102 , N120 , N165 , N166 , N89 ,   N101 , N167 , N103 , I_1_E2RQ , N130 , I_1_N292 , N168 , N104 , I_0_E2RQ ,   N135 , I_1_ECNT_E , I_1_ECNT_E434 , I_1_N256 , N170 , N169 , N175 ,   I_0_CLREVENT , N173 , N172 , N171 , N174 , N176 , N177 , N96 , N179 , N178 ,   N183 , N180 , N181 , N182 , N184 , N186 , N185 , N187 , N189 , N188 , N190 ,   I_1_CLREVENT , N193 , N192 , N191 , N195 , N194 , N196 , N200 , N93 , N198 ,   N197 , N199 , N201 , N202 , N91 , N205 , I_1_CLRZERO , N203 , N204 , N109 ,   N116 , N206 , N207 , N86 , N108 , N208 , N210 , N209 , N211 , I_1_CLRZERO309   , I_1_N310 , N212 , N213 , N214 , I_0_E2RQ562 , N215 , N216 , I_0_N274 ,   I_0_CLREVENT273 , I_0_N247 , N217 , N218 , N219 , I_1_E2RQ562 , N220 , N221 ,   I_1_N274 , I_1_CLREVENT273 , I_1_N247 , N222 , N223 , N224 , N115 , N227 ,   N226 , N225 , N110 , N229 , N228 , N230 , N234 , N232 , N231 , N233 , N236 ,   N235 , N106 , N240 , N238 , N237 , N105 , N239 , N242 , N241 , N244 , N243 ,   N245 , N248 , N247 , N246 , N100 , N249 , N251 , N250 , N99 , N255 , N253 ,   N252 , N98 , N254 , N256 , N260 , N258 , N257 , N259 , N261 , N262 ,   I_0_ZCNT_E , N263 , N264 , I_1_ZCNT_E , N266 , N265 , N267 , N268 , N271 ,   N270 , N269 , N272 , N273 , N274 , N275 , N277 , N276 , N278 , N279 , N280 ,   N281 , N282 , N283 , N286 , N285 , N284 , N289 , N288 , N287 , N295 , N290 ,   N291 , N294 , N293 , N292 , N298 , N297 , N296 , N304 , N299 , N300 , N303 ,   N302 , N301 , N307 , N306 , N305 , N312 , N309 , N308 , N311 , N310 , N313 ,   N314 , N317 , N315 , N316 , N318 , N319 , N322 , N321 , N320 , N327 , N324 ,   N323 , N326 , N325 , N328 , N329 , N332 , N330 , N331 , N333 , N334 ,   I_0_CLRZERO_REG_GSR_OR , I_0_EQ2_REG_GSR_OR , I_0_ST_INT_REG_GSR_OR ,   I_0_ECNT_E_REG_GSR_OR , I_0_ECNT_REG_0_GSR_OR , I_1_ST_INT_REG_GSR_OR ,   I_1_ECNT_E_REG_GSR_OR , I_0_ECNT_REG_2_GSR_OR , I_0_ECNT_REG_1_GSR_OR ,   I_0_ZCNT_REG_1_GSR_OR , I_0_ZCNT_REG_0_GSR_OR , I_0_ZCNT_REG_2_GSR_OR ,   I_1_ECNT_REG_1_GSR_OR , I_1_ECNT_REG_0_GSR_OR , I_1_ECNT_REG_2_GSR_OR ,   I_1_ZCNT_REG_2_GSR_OR , I_1_ZCNT_REG_1_GSR_OR , I_1_ZCNT_REG_0_GSR_OR ,   I_1_CLRZERO_REG_GSR_OR , I_0_E2RQ_REG_GSR_OR , I_1_E2RQ_REG_GSR_OR ,   I_0_ECNT_REG_4_GSR_OR , I_0_DCNT_REG_2_GSR_OR , I_0_DCNT_REG_0_GSR_OR ,   I_0_ZCNT_REG_6_GSR_OR , I_0_ZCNT_REG_4_GSR_OR , I_1_EQ2_REG_GSR_OR ,   I_1_ECNT_REG_4_GSR_OR , I_1_ZCNT_REG_6_GSR_OR , I_1_ZCNT_REG_4_GSR_OR ,   I_1_DCNT_REG_2_GSR_OR , I_1_DCNT_REG_0_GSR_OR , I_0_ZCNT_E_REG_GSR_OR ,   I_1_ZCNT_E_REG_GSR_OR , I_0_ECNT_REG_3_GSR_OR , I_0_DCNT_REG_1_GSR_OR ,   I_0_ZCNT_REG_3_GSR_OR , I_0_ZCNT_REG_5_GSR_OR , I_1_ECNT_REG_3_GSR_OR ,   I_1_ZCNT_REG_3_GSR_OR , I_1_ZCNT_REG_5_GSR_OR , I_1_DCNT_REG_1_GSR_OR ,   I_0_CLREVENT_REG_GSR_OR , I_1_CLREVENT_REG_GSR_OR , U163_1I20_GTS_TRI ,   U164_1I20_GTS_TRI , U159_CLKIO_BUFSIG , U170_2_0 , U173_2_0 , U175_2_0 ,   U177_2_0 , U181_2_0 , U184_2_0 , U185_2_0 , U185_2_1 , U186_2_0 , U186_2_1 ,   U189_2_0 , U189_2_1 , U192_2_0 , U192_2_1 , U194_2_0 , U194_2_1 , U195_2_0 ,   U195_2_1 , U197_2_0 , U197_2_1 , U198_2_0 , U198_2_1 , U214_2_0 , U235_2_0 ,   U238_2_0 , U238_2_1 , U241_2_0 , U241_2_1 , U262_2_0 , U264_2_0 , U271_2_0 ,   U283_2_0 , U283_2_1 , U284_2_0 , U284_2_1 , U287_2_0 , U290_2_0 , U292_2_0 ,   U309_2_0 , U311_2_0 , U313_2_0 , U315_2_0 , U319_2_0 , U322_2_0 , U327_2_0 ,   U330_2_0 , U334_2_0 , U337_2_0 , U340_2_0 , U343_2_0 , U352_2_0 , U352_2_1 ,   U363_2_0 , U363_2_1 , U374_2_0 , U383_2_0 , U386_2_0 , U387_2_0 , U387_2_1 ,   U395_2_0 , U404_2_0 , U407_2_0 , U408_2_0 , U408_2_1 , U176_2_INV ,   U201_2_INV , U203_2_INV , U204_2_INV , U205_2_INV , U206_2_INV , U213_2_INV ,   U218_2_INV , U219_2_INV , U222_2_INV , U224_2_INV , U225_2_INV , U226_2_INV ,   U227_2_INV , U234_2_INV , U245_2_INV , U246_2_INV , U249_2_INV , U250_2_INV ,   U253_2_INV , U256_2_INV , U257_2_INV , U260_2_INV , U263_2_INV , U267_2_INV ,   U268_2_INV , U269_2_INV , U273_2_INV , U285_2_INV , U288_2_INV , U294_2_INV ,   U295_2_INV , U296_2_INV , U304_2_INV , U318_2_INV , U323_2_INV , U324_2_INV ,   U333_2_INV , U344_2_INV , U345_2_INV , U348_2_INV , U355_2_INV , U356_2_INV ,   U359_2_INV , U366_2_INV , U367_2_INV , U370_2_INV , U376_2_INV , U380_2_INV ,   U384_2_INV , U391_2_INV , U397_2_INV , U401_2_INV , U405_2_INV ,   U170_N153_2_INV , U175_N157_2_INV , U181_N160_2_INV , U185_N122_2_INV ,   U186_N118_2_INV , U189_N102_2_INV , U192_N101_2_INV , U194_N103_2_INV ,   U197_N104_2_INV , U214_N182_2_INV , U235_N205_2_INV , U238_N109_2_INV ,   U241_N108_2_INV , U262_N223_2_INV , U283_I_0_EQ2282_2_INV ,   U284_I_1_EQ2282_2_INV , U309_N139_2_INV , U311_N89_2_INV , U313_N140_2_INV ,   U315_N86_2_INV , U352_N295_2_INV , U363_N304_2_INV , U383_N317_2_INV ,   U404_N332_2_INV , U163_1I20_GTS_TRI_2_INV , U164_1I20_GTS_TRI_2_INV , GND ,   GSR , GTS : STD_LOGIC ;  signal I_1_N265 : STD_LOGIC_VECTOR ( 0 downto 0 );  signal I_0_N265 : STD_LOGIC_VECTOR ( 0 downto 0 );  signal I_0_ZCNT : STD_LOGIC_VECTOR ( 4 downto 0 );  signal I_0_LT_114_LT_LT_AEQB : STD_LOGIC_VECTOR ( 6 downto 2 );  signal I_0_ECNT : STD_LOGIC_VECTOR ( 4 downto 0 );  signal I_1_ECNT : STD_LOGIC_VECTOR ( 4 downto 0 );  signal I_0_ECNT462 : STD_LOGIC_VECTOR ( 0 downto 0 );  signal I_0_N319 : STD_LOGIC_VECTOR ( 0 downto 0 );  signal I_0_N328 : STD_LOGIC_VECTOR ( 0 downto 0 );  signal I_1_N319 : STD_LOGIC_VECTOR ( 0 downto 0 );  signal I_1_ZCNT : STD_LOGIC_VECTOR ( 4 downto 0 );  signal I_1_LT_114_LT_LT_AEQB : STD_LOGIC_VECTOR ( 6 downto 2 );  signal I_1_N328 : STD_LOGIC_VECTOR ( 0 downto 0 );  signal I_0_DCNT : STD_LOGIC_VECTOR ( 2 downto 0 );  signal I_1_DCNT : STD_LOGIC_VECTOR ( 2 downto 0 );  begin    U156 : X_BUF       port map ( I => A_CHECK , O => N14 ) ;    U157 : X_BUF       port map ( I => B_CHECK , O => N15 ) ;    U158 : X_BUF       port map ( I => RESET , O => N16 ) ;    U160 : X_BUF       port map ( I => CLKEN , O => N18 ) ;    U161 : X_BUF       port map ( I => A_TICK , O => N19 ) ;    U162 : X_BUF       port map ( I => B_TICK , O => N20 ) ;    U165 : X_INV       port map ( I => N16 , O => I_0_N1163 ) ;    U166 : X_INV       port map ( I => N335 , O => I_0_ST_INT446 ) ;    U167 : X_INV       port map ( I => N336 , O => I_1_ST_INT446 ) ;    U168 : X_INV       port map ( I => N153 , O => N154 ) ;    U169 : X_INV       port map ( I => N336 , O => N152 ) ;    U171 : X_OR2       port map ( I0 => I_1_EQ2282 , I1 => N154 , O => I_1_N283 ) ;    U172 : X_OR2       port map ( I0 => N140 , I1 => N20 , O => N155 ) ;    I_0_CLRZERO_REG : X_FF       port map ( I => I_0_CLRZERO309 , CLK => N17 , CE => I_0_N310 , SET => GND       , RST => I_0_CLRZERO_REG_GSR_OR , O => I_0_CLRZERO ) ;    U174 : X_INV       port map ( I => N139 , O => N156 ) ;    U176 : X_AND2       port map ( I0 => N157 , I1 => I_0_CLRZERO309 , O => U176_2_INV ) ;    U178 : X_AND2       port map ( I0 => N158 , I1 => N119 , O => N94 ) ;    I_0_EQ2_REG : X_FF       port map ( I => I_0_EQ2282 , CLK => N17 , CE => I_0_N283 , SET => GND ,       RST => I_0_EQ2_REG_GSR_OR , O => I_0_EQ2 ) ;    U179 : X_INV       port map ( I => N160 , O => N161 ) ;    U180 : X_INV       port map ( I => N335 , O => N159 ) ;    U182 : X_OR2       port map ( I0 => I_0_EQ2282 , I1 => N161 , O => I_0_N283 ) ;    U183 : X_OR2       port map ( I0 => N139 , I1 => N19 , O => N162 ) ;    I_0_ST_INT_REG : X_FF       port map ( I => I_0_ST_INT446 , CLK => N17 , CE => I_0_N292 , SET => GND       , RST => I_0_ST_INT_REG_GSR_OR , O => N335 ) ;    I_0_ECNT_E_REG : X_FF       port map ( I => I_0_ECNT_E434 , CLK => N17 , CE => I_0_N256 , SET => GND       , RST => I_0_ECNT_E_REG_GSR_OR , O => I_0_ECNT_E ) ;    U187 : X_INV       port map ( I => N335 , O => N163 ) ;    U188 : X_INV       port map ( I => I_0_ECNT(4) , O => N164 ) ;    U190 : X_INV       port map ( I => N122 , O => N165 ) ;    U191 : X_INV       port map ( I => N89 , O => N166 ) ;    I_0_ECNT_REG_0_Q : X_FF       port map ( I => I_0_ECNT462(0) , CLK => N17 , CE => I_0_N319(0) ,       SET => GND , RST => I_0_ECNT_REG_0_GSR_OR , O => I_0_ECNT(0) ) ;    U193 : X_INV       port map ( I => I_1_ECNT(0) , O => N167 ) ;    I_1_ST_INT_REG : X_FF       port map ( I => I_1_ST_INT446 , CLK => N17 , CE => I_1_N292 , SET => GND       , RST => I_1_ST_INT_REG_GSR_OR , O => N336 ) ;    U196 : X_INV       port map ( I => I_0_ECNT(0) , O => N168 ) ;    I_1_ECNT_E_REG : X_FF       port map ( I => I_1_ECNT_E434 , CLK => N17 , CE => I_1_N256 , SET => GND       , RST => I_1_ECNT_E_REG_GSR_OR , O => I_1_ECNT_E ) ;    U199 : X_INV       port map ( I => N169 , O => N170 ) ;    U200 : X_XOR2       port map ( I0 => I_0_ECNT(1) , I1 => I_0_ECNT(0) , O => N169 ) ;    U201 : X_OR2       port map ( I0 => N170 , I1 => I_0_CLREVENT , O => U201_2_INV ) ;    U202 : X_INV       port map ( I => N172 , O => N173 ) ;    U203 : X_AND2       port map ( I0 => I_0_ECNT(0) , I1 => I_0_ECNT(1) , O => U203_2_INV ) ;    U204 : X_XOR2       port map ( I0 => I_0_ECNT(2) , I1 => N171 , O => U204_2_INV ) ;    U205 : X_OR2       port map ( I0 => N173 , I1 => I_0_CLREVENT , O => U205_2_INV ) ;    I_0_ECNT_REG_2_Q : X_FF       port map ( I => N174 , CLK => N17 , CE => I_0_N319(0) , SET => GND ,       RST => I_0_ECNT_REG_2_GSR_OR , O => I_0_ECNT(2) ) ;    I_0_ECNT_REG_1_Q : X_FF       port map ( I => N175 , CLK => N17 , CE => I_0_N319(0) , SET => GND ,       RST => I_0_ECNT_REG_1_GSR_OR , O => I_0_ECNT(1) ) ;    U206 : X_OR2       port map ( I0 => I_0_CLREVENT , I1 => I_0_ECNT(0) , O => U206_2_INV ) ;    U207 : X_XOR2       port map ( I0 => I_0_ZCNT(1) , I1 => I_0_ZCNT(0) , O => N176 ) ;    U208 : X_AND2       port map ( I0 => N176 , I1 => N96 , O => N177 ) ;    I_0_ZCNT_REG_1_Q : X_FF       port map ( I => N177 , CLK => N17 , CE => I_0_N328(0) , SET => GND ,       RST => I_0_ZCNT_REG_1_GSR_OR , O => I_0_ZCNT(1) ) ;    U209 : X_XOR2       port map ( I0 => N178 , I1 => I_0_LT_114_LT_LT_AEQB(2) , O => N179 ) ;    U210 : X_AND2       port map ( I0 => I_0_ZCNT(0) , I1 => I_0_ZCNT(1) , O => N178 ) ;    U211 : X_AND2       port map ( I0 => N179 , I1 => N96 , O => N183 ) ;    U212 : X_INV       port map ( I => N14 , O => N180 ) ;    U213 : X_OR2       port map ( I0 => N94 , I1 => N180 , O => U213_2_INV ) ;    I_0_ZCNT_REG_0_Q : X_FF       port map ( I => N182 , CLK => N17 , CE => I_0_N328(0) , SET => GND ,       RST => I_0_ZCNT_REG_0_GSR_OR , O => I_0_ZCNT(0) ) ;    I_0_ZCNT_REG_2_Q : X_FF       port map ( I => N183 , CLK => N17 , CE => I_0_N328(0) , SET => GND ,       RST => I_0_ZCNT_REG_2_GSR_OR , O => I_0_LT_114_LT_LT_AEQB(2) ) ;    U215 : X_INV       port map ( I => N186 , O => N184 ) ;    U216 : X_INV       port map ( I => N94 , O => N185 ) ;    U217 : X_OR2       port map ( I0 => N184 , I1 => I_0_CLRZERO , O => N187 ) ;    U218 : X_AND2       port map ( I0 => N185 , I1 => N14 , O => U218_2_INV ) ;    U219 : X_AND2       port map ( I0 => N187 , I1 => N18 , O => U219_2_INV ) ;    U220 : X_INV       port map ( I => N188 , O => N189 ) ;