?? time_sim.vhd
字號:
U221 : X_XOR2 port map ( I0 => I_1_ECNT(1) , I1 => I_1_ECNT(0) , O => N188 ) ; U222 : X_OR2 port map ( I0 => N189 , I1 => I_1_CLREVENT , O => U222_2_INV ) ; I_1_ECNT_REG_1_Q : X_FF port map ( I => N190 , CLK => N17 , CE => I_1_N319(0) , SET => GND , RST => I_1_ECNT_REG_1_GSR_OR , O => I_1_ECNT(1) ) ; U223 : X_INV port map ( I => N192 , O => N193 ) ; U224 : X_AND2 port map ( I0 => I_1_ECNT(0) , I1 => I_1_ECNT(1) , O => U224_2_INV ) ; U225 : X_XOR2 port map ( I0 => I_1_ECNT(2) , I1 => N191 , O => U225_2_INV ) ; U226 : X_OR2 port map ( I0 => N193 , I1 => I_1_CLREVENT , O => U226_2_INV ) ; U227 : X_OR2 port map ( I0 => I_1_CLREVENT , I1 => I_1_ECNT(0) , O => U227_2_INV ) ; I_1_ECNT_REG_0_Q : X_FF port map ( I => N194 , CLK => N17 , CE => I_1_N319(0) , SET => GND , RST => I_1_ECNT_REG_0_GSR_OR , O => I_1_ECNT(0) ) ; I_1_ECNT_REG_2_Q : X_FF port map ( I => N195 , CLK => N17 , CE => I_1_N319(0) , SET => GND , RST => I_1_ECNT_REG_2_GSR_OR , O => I_1_ECNT(2) ) ; U228 : X_XOR2 port map ( I0 => I_1_ZCNT(1) , I1 => I_1_ZCNT(0) , O => N196 ) ; U229 : X_AND2 port map ( I0 => N196 , I1 => N93 , O => N200 ) ; U230 : X_XOR2 port map ( I0 => N197 , I1 => I_1_LT_114_LT_LT_AEQB(2) , O => N198 ) ; U231 : X_AND2 port map ( I0 => I_1_ZCNT(0) , I1 => I_1_ZCNT(1) , O => N197 ) ; U232 : X_AND2 port map ( I0 => N198 , I1 => N93 , O => N199 ) ; I_1_ZCNT_REG_2_Q : X_FF port map ( I => N199 , CLK => N17 , CE => I_1_N328(0) , SET => GND , RST => I_1_ZCNT_REG_2_GSR_OR , O => I_1_LT_114_LT_LT_AEQB(2) ) ; I_1_ZCNT_REG_1_Q : X_FF port map ( I => N200 , CLK => N17 , CE => I_1_N328(0) , SET => GND , RST => I_1_ZCNT_REG_1_GSR_OR , O => I_1_ZCNT(1) ) ; U233 : X_INV port map ( I => N15 , O => N201 ) ; U234 : X_OR2 port map ( I0 => N91 , I1 => N201 , O => U234_2_INV ) ; U236 : X_INV port map ( I => N336 , O => N203 ) ; U237 : X_INV port map ( I => I_1_ECNT(4) , O => N204 ) ; I_1_ZCNT_REG_0_Q : X_FF port map ( I => N205 , CLK => N17 , CE => I_1_N328(0) , SET => GND , RST => I_1_ZCNT_REG_0_GSR_OR , O => I_1_ZCNT(0) ) ; U239 : X_INV port map ( I => N118 , O => N206 ) ; U240 : X_INV port map ( I => N86 , O => N207 ) ; U242 : X_INV port map ( I => N210 , O => N208 ) ; U243 : X_INV port map ( I => N91 , O => N209 ) ; U244 : X_OR2 port map ( I0 => N208 , I1 => I_1_CLRZERO , O => N211 ) ; U245 : X_AND2 port map ( I0 => N209 , I1 => N15 , O => U245_2_INV ) ; U246 : X_AND2 port map ( I0 => N211 , I1 => N18 , O => U246_2_INV ) ; I_1_CLRZERO_REG : X_FF port map ( I => I_1_CLRZERO309 , CLK => N17 , CE => I_1_N310 , SET => GND , RST => I_1_CLRZERO_REG_GSR_OR , O => I_1_CLRZERO ) ; U247 : X_INV port map ( I => N213 , O => N212 ) ; U248 : X_OR2 port map ( I0 => N212 , I1 => I_0_EQ2 , O => N214 ) ; U249 : X_AND2 port map ( I0 => N122 , I1 => N89 , O => U249_2_INV ) ; U250 : X_AND2 port map ( I0 => N214 , I1 => N19 , O => U250_2_INV ) ; U251 : X_INV port map ( I => I_0_N265(0) , O => N215 ) ; U252 : X_OR2 port map ( I0 => I_0_ECNT_E434 , I1 => N215 , O => N216 ) ; U253 : X_AND2 port map ( I0 => N216 , I1 => I_0_CLREVENT273 , O => U253_2_INV ) ; I_0_E2RQ_REG : X_FF port map ( I => I_0_E2RQ562 , CLK => N17 , CE => I_0_N247 , SET => GND , RST => I_0_E2RQ_REG_GSR_OR , O => I_0_E2RQ ) ; U254 : X_INV port map ( I => N218 , O => N217 ) ; U255 : X_OR2 port map ( I0 => N217 , I1 => I_1_EQ2 , O => N219 ) ; U256 : X_AND2 port map ( I0 => N118 , I1 => N86 , O => U256_2_INV ) ; U257 : X_AND2 port map ( I0 => N219 , I1 => N20 , O => U257_2_INV ) ; U258 : X_INV port map ( I => I_1_N265(0) , O => N220 ) ; U259 : X_OR2 port map ( I0 => I_1_ECNT_E434 , I1 => N220 , O => N221 ) ; U260 : X_AND2 port map ( I0 => N221 , I1 => I_1_CLREVENT273 , O => U260_2_INV ) ; I_1_E2RQ_REG : X_FF port map ( I => I_1_E2RQ562 , CLK => N17 , CE => I_1_N247 , SET => GND , RST => I_1_E2RQ_REG_GSR_OR , O => I_1_E2RQ ) ; U261 : X_INV port map ( I => N140 , O => N222 ) ; U263 : X_AND2 port map ( I0 => N223 , I1 => I_1_CLRZERO309 , O => U263_2_INV ) ; U265 : X_AND2 port map ( I0 => N224 , I1 => N115 , O => N91 ) ; U266 : X_INV port map ( I => N226 , O => N227 ) ; U267 : X_AND2 port map ( I0 => N110 , I1 => I_0_ECNT(3) , O => U267_2_INV ) ; U268 : X_XOR2 port map ( I0 => I_0_ECNT(4) , I1 => N225 , O => U268_2_INV ) ; U269 : X_OR2 port map ( I0 => N227 , I1 => I_0_CLREVENT , O => U269_2_INV ) ; U270 : X_OR2 port map ( I0 => N108 , I1 => N109 , O => N228 ) ; I_0_ECNT_REG_4_Q : X_FF port map ( I => N229 , CLK => N17 , CE => I_0_N319(0) , SET => GND , RST => I_0_ECNT_REG_4_GSR_OR , O => I_0_ECNT(4) ) ; U272 : X_INV port map ( I => I_0_ECNT_E434 , O => N230 ) ; U273 : X_OR2 port map ( I0 => I_0_DCNT(0) , I1 => N230 , O => U273_2_INV ) ; U274 : X_XOR2 port map ( I0 => N231 , I1 => I_0_DCNT(2) , O => N232 ) ; U275 : X_AND2 port map ( I0 => I_0_DCNT(0) , I1 => I_0_DCNT(1) , O => N231 ) ; U276 : X_AND2 port map ( I0 => N232 , I1 => I_0_ECNT_E434 , O => N233 ) ; I_0_DCNT_REG_2_Q : X_FF port map ( I => N233 , CLK => N17 , CE => I_0_N265(0) , SET => GND , RST => I_0_DCNT_REG_2_GSR_OR , O => I_0_DCNT(2) ) ; I_0_DCNT_REG_0_Q : X_FF port map ( I => N234 , CLK => N17 , CE => I_0_N265(0) , SET => GND , RST => I_0_DCNT_REG_0_GSR_OR , O => I_0_DCNT(0) ) ; U277 : X_XOR2 port map ( I0 => N235 , I1 => I_0_ZCNT(4) , O => N236 ) ; U278 : X_AND2 port map ( I0 => N106 , I1 => I_0_ZCNT(3) , O => N235 ) ; U279 : X_AND2 port map ( I0 => N236 , I1 => N96 , O => N240 ) ; U280 : X_XOR2 port map ( I0 => N237 , I1 => I_0_LT_114_LT_LT_AEQB(6) , O => N238 ) ; U281 : X_AND2 port map ( I0 => N105 , I1 => I_0_LT_114_LT_LT_AEQB(5) , O => N237 ) ; U282 : X_AND2 port map ( I0 => N238 , I1 => N96 , O => N239 ) ; I_0_ZCNT_REG_6_Q : X_FF port map ( I => N239 , CLK => N17 , CE => I_0_N328(0) , SET => GND , RST => I_0_ZCNT_REG_6_GSR_OR , O => I_0_LT_114_LT_LT_AEQB(6) ) ; I_0_ZCNT_REG_4_Q : X_FF port map ( I => N240 , CLK => N17 , CE => I_0_N328(0) , SET => GND , RST => I_0_ZCNT_REG_4_GSR_OR , O => I_0_ZCNT(4) ) ; I_1_EQ2_REG : X_FF port map ( I => I_1_EQ2282 , CLK => N17 , CE => I_1_N283 , SET => GND , RST => I_1_EQ2_REG_GSR_OR , O => I_1_EQ2 ) ; U285 : X_AND2 port map ( I0 => I_1_E2RQ562 , I1 => I_1_E2RQ , O => U285_2_INV ) ; U286 : X_INV port map ( I => N336 , O => N241 ) ; U288 : X_AND2 port map ( I0 => I_0_E2RQ562 , I1 => I_0_E2RQ , O => U288_2_INV ) ; U289 : X_INV port map ( I => N335 , O => N243 ) ; U291 : X_OR2 port map ( I0 => N101 , I1 => N102 , O => N245 ) ; U293 : X_INV port map ( I => N247 , O => N248 ) ; U294 : X_AND2 port map ( I0 => N100 , I1 => I_1_ECNT(3) , O => U294_2_INV ) ; U295 : X_XOR2 port map ( I0 => I_1_ECNT(4) , I1 => N246 , O => U295_2_INV ) ; U296 : X_OR2 port map ( I0 => N248 , I1 => I_1_CLREVENT , O => U296_2_INV ) ; I_1_ECNT_REG_4_Q : X_FF port map ( I => N249 , CLK => N17 , CE => I_1_N319(0) , SET => GND , RST => I_1_ECNT_REG_4_GSR_OR , O => I_1_ECNT(4) ) ; U297 : X_XOR2 port map ( I0 => N250 , I1 => I_1_ZCNT(4) , O => N251 ) ; U298 : X_AND2 port map ( I0 => N99 , I1 => I_1_ZCNT(3) , O => N250 ) ; U299 : X_AND2 port map ( I0 => N251 , I1 => N93 , O => N255 ) ; U300 : X_XOR2 port map ( I0 => N252 , I1 => I_1_LT_114_LT_LT_AEQB(6) , O => N253 ) ; U301 : X_AND2 port map ( I0 => N98 , I1 => I_1_LT_114_LT_LT_AEQB(5) , O => N252 ) ; U302 : X_AND2 port map ( I0 => N253 , I1 => N93 , O => N254 ) ; I_1_ZCNT_REG_6_Q : X_FF port map ( I => N254 , CLK => N17 , CE => I_1_N328(0) , SET => GND , RST => I_1_ZCNT_REG_6_GSR_OR , O => I_1_LT_114_LT_LT_AEQB(6) ) ; I_1_ZCNT_REG_4_Q : X_FF port map ( I => N255 , CLK => N17 , CE => I_1_N328(0) , SET => GND , RST => I_1_ZCNT_REG_4_GSR_OR , O => I_1_ZCNT(4) ) ; U303 : X_INV port map ( I => I_1_ECNT_E434 , O => N256 ) ; U304 : X_OR2 port map ( I0 => I_1_DCNT(0) , I1 => N256 , O => U304_2_INV ) ; U305 : X_XOR2 port map ( I0 => N257 , I1 => I_1_DCNT(2) , O => N258 ) ; U306 : X_AND2 port map ( I0 => I_1_DCNT(0) , I1 => I_1_DCNT(1) , O => N257 ) ; U307 : X_AND2 port map ( I0 => N258 , I1 => I_1_ECNT_E434 , O => N259 ) ; I_1_DCNT_REG_2_Q : X_FF port map ( I => N259 , CLK => N17 , CE => I_1_N265(0) , SET => GND , RST => I_1_DCNT_REG_2_GSR_OR , O => I_1_DCNT(2) ) ; I_1_DCNT_REG_0_Q : X_FF port map ( I => N260 , CLK => N17 , CE => I_1_N265(0) , SET => GND , RST => I_1_DCNT_REG_0_GSR_OR , O => I_1_DCNT(0) ) ; U308 : X_INV port map ( I => I_0_DCNT(2) , O => N261 ) ; U310 : X_INV port map ( I => I_0_DCNT(2) , O => N262 ) ; I_0_ZCNT_E_REG : X_FF port map ( I => N139 , CLK => N17 , CE => I_0_N301 , SET => GND , RST => I_0_ZCNT_E_REG_GSR_OR , O => I_0_ZCNT_E ) ; U312 : X_INV port map ( I => I_1_DCNT(2) , O => N263 ) ; U314 : X_INV port map ( I => I_1_DCNT(2) , O => N264 ) ; I_1_ZCNT_E_REG : X_FF port map ( I => N140 , CLK => N17 , CE => I_1_N301 , SET => GND , RST => I_1_ZCNT_E_REG_GSR_OR , O => I_1_ZCNT_E ) ; U316 : X_INV port map ( I => N265 , O => N266 ) ; U317 : X_XOR2 port map ( I0 => N110 , I1 => I_0_ECNT(3) , O => N265 ) ; U318 : X_OR2 port map ( I0 => N266 , I1 => I_0_CLREVENT , O => U318_2_INV ) ; I_0_ECNT_REG_3_Q : X_FF port map ( I => N267 , CLK => N17 , CE => I_0_N319(0) , SET => GND , RST => I_0_ECNT_REG_3_GSR_OR , O => I_0_ECNT(3) ) ; U320 : X_XOR2 port map ( I0 => I_0_DCNT(1) , I1 => I_0_DCNT(0) , O => N268 ) ; U321 : X_AND2 port map ( I0 => N268 , I1 => I_0_ECNT_E434 , O => N271 ) ; U323 : X_AND2 port map ( I0 => N335 , I1 => N139 , O => U323_2_INV ) ; U324 : X_AND2 port map ( I0 => N269 , I1 => N270 , O => U324_2_INV ) ; I_0_DCNT_REG_1_Q : X_FF port map ( I => N271 , CLK => N17 , CE => I_0_N265(0) , SET => GND , RST => I_0_DCNT_REG_1_GSR_OR , O => I_0_DCNT(1) ) ; U325 : X_XOR2 port map ( I0 => N106 , I1 => I_0_ZCNT(3) , O => N272 ) ; U326 : X_AND2 port map ( I0 => N272 , I1 => N96 , O => N273 ) ; I_0_ZCNT_REG_3_Q : X_FF port map ( I => N273 , CLK => N17 , CE => I_0_N328(0) , SET => GND , RST => I_0_ZCNT_REG_3_GSR_OR , O => I_0_ZCNT(3) ) ; U328 : X_XOR2 port map ( I0 => N105 , I1 => I_0_LT_114_LT_LT_AEQB(5) , O => N274 ) ; U329 : X_AND2 port map ( I0 => N274 , I1 => N96 , O => N275 ) ; I_0_ZCNT_REG_5_Q : X_FF port map ( I => N275 , CLK => N17 , CE => I_0_N328(0) , SET => GND , RST => I_0_ZCNT_REG_5_GSR_OR , O => I_0_LT_114_LT_LT_AEQB(5) ) ; U331 : X_INV port map ( I => N276 , O => N277 ) ; U332 : X_XOR2 port map ( I0 => N100 , I1 => I_1_ECNT(3) , O => N276 ) ; U333 : X_OR2 port map ( I0 => N277 , I1 => I_1_CLREVENT , O => U333_2_INV ) ; I_1_ECNT_REG_3_Q : X_FF port map ( I => N278 , CLK => N17 , CE => I_1_N319(0) , SET => GND , RST => I_1_ECNT_REG_3_GSR_OR , O => I_1_ECNT(3) ) ; U335 : X_XOR2 port map ( I0 => N99 , I1 => I_1_ZCNT(3) , O => N279 ) ; U336 : X_AND2 port map ( I0 => N279 , I1 => N93 , O => N280 ) ; I_1_ZCNT_REG_3_Q : X_FF port map ( I => N280 , CLK => N17 , CE => I_1_N328(0) , SET => GND , RST => I_1_ZCNT_REG_3_GSR_OR , O => I_1_ZCNT(3) ) ; U338 : X_XOR2 port map ( I0 => N98 , I1 => I_1_LT_114_LT_LT_AEQB(5) , O => N281 ) ; U339 : X_AND2 port map ( I0 => N281 , I1 => N93 , O => N282 ) ; I_1_ZCNT_REG_5_Q : X_FF port map ( I => N282 , CLK => N17 , CE => I_1_N328(0) , SET => GND , RST => I_1_ZCNT_REG_5_GSR_OR , O => I_1_LT_114_LT_LT_AEQB(5) ) ; U341 : X_XOR2 port map ( I0 => I_1_DCNT(1) , I1 => I_1_DCNT(0) , O => N283 ) ; U342 : X_AND2 port map ( I0 => N283 , I1 => I_1_ECNT_E434 , O => N286 ) ; U344 : X_AND2 port map ( I0 => N336 , I1 => N140 , O => U344_2_INV ) ; U345 : X_AND2 port map ( I0 => N284 , I1 => N285 , O => U345_2_INV ) ; I_1_DCNT_REG_1_Q : X_FF port map ( I => N286 , CLK => N17 , CE => I_1_N265(0) , SET => GND , RST => I_1_DCNT_REG_1_GSR_OR , O => I_1_DCNT(1) ) ; U346 : X_INV port map ( I => N288 , O => N289 ) ; U347 : X_INV port map ( I => N96 , O => N287 ) ; U348 : X_AND2 port map ( I0 => N287 , I1 => N18 , O => U348_2_INV ) ; U349 : X_OR2 port map ( I0 => N295 , I1 => N289 , O => I_0_N328(0) ) ; U350 : X_INV port map ( I => N18 , O => N290 ) ;?? 快捷鍵說明
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