?? time_sim.sdf
字號:
(CELL (CELLTYPE "X_XOR2") (INSTANCE U225) (DELAY (ABSOLUTE (PORT I0 (1598:1598:1598) (1598:1598:1598)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U226) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (1094:1094:1094) (1094:1094:1094)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U227) (DELAY (ABSOLUTE (PORT I0 (1115:1115:1115) (1115:1115:1115)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (1199:1199:1199) (1199:1199:1199)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ECNT_REG_0_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1247:1247:1247) (1247:1247:1247)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4048:4048:4048) (4048:4048:4048)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ECNT_REG_2_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1247:1247:1247) (1247:1247:1247)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4027:4027:4027) (4027:4027:4027)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_XOR2") (INSTANCE U228) (DELAY (ABSOLUTE (PORT I0 (1230:1230:1230) (1230:1230:1230)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1094:1094:1094) (1094:1094:1094)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U229) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (1356:1356:1356) (1356:1356:1356)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_XOR2") (INSTANCE U230) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1193:1193:1193) (1193:1193:1193)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U231) (DELAY (ABSOLUTE (PORT I0 (1492:1492:1492) (1492:1492:1492)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1368:1368:1368) (1368:1368:1368)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U232) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (2420:2420:2420) (2420:2420:2420)) (PORT I1 (1431:1431:1431) (1431:1431:1431)) (IOPATH I1 O (2420:2420:2420) (2420:2420:2420)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ZCNT_REG_2_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1247:1247:1247) (1247:1247:1247)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4584:4584:4584) (4584:4584:4584)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ZCNT_REG_1_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1266:1266:1266) (1266:1266:1266)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4280:4280:4280) (4280:4280:4280)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U233) (DELAY (ABSOLUTE (PORT I (2123:2123:2123) (2123:2123:2123)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U234) (DELAY (ABSOLUTE (PORT I0 (1504:1504:1504) (1504:1504:1504)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U236) (DELAY (ABSOLUTE (PORT I (1468:1468:1468) (1468:1468:1468)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U237) (DELAY (ABSOLUTE (PORT I (1787:1787:1787) (1787:1787:1787)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_ZCNT_REG_0_Q) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (PORT CLK (1266:1266:1266) (1266:1266:1266)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (4280:4280:4280) (4280:4280:4280)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U239) (DELAY (ABSOLUTE (PORT I (1317:1317:1317) (1317:1317:1317)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U240) (DELAY (ABSOLUTE (PORT I (1942:1942:1942) (1942:1942:1942)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U242) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U243) (DELAY (ABSOLUTE (PORT I (1107:1107:1107) (1107:1107:1107)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U244) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1098:1098:1098) (1098:1098:1098)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U245) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1760:1760:1760) (1760:1760:1760)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U246) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (1600:1600:1600) (1600:1600:1600)) (PORT I1 (5627:5627:5627) (5627:5627:5627)) (IOPATH I1 O (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_1_CLRZERO_REG) (DELAY (ABSOLUTE (PORT I (820:820:820) (820:820:820)) (PORT CLK (1266:1266:1266) (1266:1266:1266)) (IOPATH CLK O (2820:2820:2820) (0:0:0)) (PORT CE (3667:3667:3667) (3667:3667:3667)) (IOPATH SET O (0:0:0) (0:0:0)) (PORT RST (0:0:0) (0:0:0)) (IOPATH RST O (0:0:0) (0:0:0)) ) ) (TIMINGCHECK (WIDTH (posedge CLK) (4000:4000:4000)) (WIDTH (negedge CLK) (4000:4000:4000)) (RECOVERY (negedge RST) (posedge CLK) (0:0:0)) (SETUP (posedge CE) (posedge CLK) (0:0:0)) (SETUP (negedge CE) (posedge CLK) (0:0:0)) (SETUP (posedge I) (posedge CLK) (0:0:0)) (SETUP (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge RST) (posedge CLK) (0:0:0)) (HOLD (negedge I) (posedge CLK) (0:0:0)) (HOLD (negedge CE) (posedge CLK) (0:0:0)) (HOLD (posedge I) (posedge CLK) (0:0:0)) (HOLD (posedge CE) (posedge CLK) (0:0:0)) (WIDTH (posedge RST) (4000:4000:4000)) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U247) (DELAY (ABSOLUTE (PORT I (0:0:0) (0:0:0)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U248) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1509:1509:1509) (1509:1509:1509)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U249) (DELAY (ABSOLUTE (PORT I0 (2192:2192:2192) (2192:2192:2192)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (1538:1538:1538) (1538:1538:1538)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U250) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (1600:1600:1600) (1600:1600:1600)) (PORT I1 (1744:1744:1744) (1744:1744:1744)) (IOPATH I1 O (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_INV") (INSTANCE U251) (DELAY (ABSOLUTE (PORT I (1214:1214:1214) (1214:1214:1214)) (IOPATH I O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_OR2") (INSTANCE U252) (DELAY (ABSOLUTE (PORT I0 (1183:1183:1183) (1183:1183:1183)) (IOPATH I0 O (0:0:0) (0:0:0)) (PORT I1 (0:0:0) (0:0:0)) (IOPATH I1 O (0:0:0) (0:0:0)) ) ) ) (CELL (CELLTYPE "X_AND2") (INSTANCE U253) (DELAY (ABSOLUTE (PORT I0 (0:0:0) (0:0:0)) (IOPATH I0 O (1600:1600:1600) (1600:1600:1600)) (PORT I1 (1173:1173:1173) (1173:1173:1173)) (IOPATH I1 O (1600:1600:1600) (1600:1600:1600)) ) ) ) (CELL (CELLTYPE "X_FF") (INSTANCE I_0_E2RQ_REG) (DELAY (ABSOLUTE (PORT I (820:820:820) (820:820:820))?? 快捷鍵說明
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