// VERILOG TestFixture Template produced by ngd2ver M1.4.12// Design file: time_sim.nga// Date:Tue Jan  6 19:58:04 1998// ATTENTION: This file was created by NGD2VER and may therefore be overwritten// by subsequent runs of NGD2VER. Xilinx recommends that you copy this file to// a new name, or 'paste' this text into another file, to avoid accidental loss// of data.`timescale 1 ns/1 psmodule test;  reg [3:0] S;  reg [15:0] A_P;  wire [15:0] B_P;  reg GTS;  `define GTS_SIGNAL test.GTS  barrel uut ( .S (S) , .A_P (A_P) , .B_P (B_P) );  initial begin    $timeformat(-9,3,"ns",12);    $shm_open("time_sim.shm");    $shm_probe("AS");  end  initial begin    $display("           T SA   B   ");    $display("           i [_   _   ");    $display("           m 3P   P   ");    $display("           e :[   [   ");    $display("             01   1   ");    $display("             ]5   5   ");    $display("              :   :   ");    $display("              0   0   ");    $display("              ]   ]   ");    $monitor("%t",$realtime,, "%h", S, "%h", A_P, "%h", B_P );  end  initial begin      `GTS_SIGNAL = 0;    #100      S = 0 ;      A_P = 0 ;    #1000 $stop;    // #1000 $finish;  endendmodule